MOVW	y+65540(FP), R4			// 1e020014de8f1000c4338028
	MOVWU	y+65540(FP), R4			// 1e020014de8f1000c433802a
	MOVV	y+65540(FP), R4			// 1e020014de8f1000c433c028
	MOVB	y+65540(FP), R4			// 1e020014de8f1000c4330028
	MOVBU	y+65540(FP), R4			// 1e020014de8f1000c433002a
	MOVW	y+4097(FP), R4			// 3e000014de8f1000c4278028
	MOVWU	y+4097(FP), R4			// 3e000014de8f1000c427802a
	MOVV	y+4097(FP), R4			// 3e000014de8f1000c427c028

	MOVVF	F4, F5			// 85181d01
	MOVF	F4, F5			// 85941401
	MOVD	F4, F5			// 85981401
	MOVW	R4, result+16(FP)	// 64608029
	MOVWU	R4, result+16(FP)	// 64608029
	MOVV	R4, result+16(FP)	// 6460c029
	MOVB	R4, result+16(FP)	// 64600029
	MOVBU	R4, result+16(FP)	// 64600029
	MOVWL	R4, result+16(FP)	// 6460002f
	MOVVL	R4, result+16(FP)	// 6460802f
	MOVW	R4, 1(R5)		// a4048029
	MOVWU	R4, 1(R5)		// a4048029
	MOVV	R4, 1(R5)		// a404c029

	// Pseudo-registers should not be used as scaled index.
	CALL (AX)(PC*1)                 // ERROR "invalid instruction"
	CALL (AX)(SB*1)                 // ERROR "invalid instruction"
	CALL (AX)(FP*1)                 // ERROR "invalid instruction"
	// Forbid memory operands for MOV CR/DR. See #24981.
	MOVQ CR0, (AX)                  // ERROR "invalid instruction"
	MOVQ CR2, (AX)                  // ERROR "invalid instruction"

	IMULL	AX
	IMULL	$4, CX
	IMULL	AX, BX

// LTYPEXC spec9	{ outcode(int($1), &$2); }
	CMPPD	X0, X1, 4
	CMPPD	foo+4(SB), X1, 4

// LTYPEX spec10	{ outcode(int($1), &$2); }
	PINSRD	$1, (AX), X0
	PINSRD	$2, foo+4(FP), X0

// Was bug: LOOP is a branch instruction.
	JCS	2(PC)
loop:
	LOOP	loop // LOOP

// Tests for TLS reference.
	MOVL    (TLS), AX
	MOVL    8(TLS), DX

// LTYPE0 nonnon	{ outcode(int($1), &$2); }

	//
	// special
	//
	SYSCALL
	BREAK
	SYNC

	//
	// conditional move on zero/nonzero gp value
	//
	CMOVN	R1, R2, R3
	CMOVZ	R1, R2, R3

	//
	// conditional move on fp false/true
	//
	CMOVF	R1, R2
	CMOVT	R1, R2

	//
	// conditional traps
	//
	TEQ	$1, R1, R2
	TEQ	$1, R1


	//
	// other
	//
	CLO	R1, R2
	SQRTD	F0, F1