SETAE:     "setnb",
	SETA:      "setnbe",
	SETGE:     "setnl",
	SETNE:     "setnz",
	SETG:      "setnle",
	SETE:      "setz",
	CMOVAE:    "cmovnb",
	CMOVA:     "cmovnbe",
	CMOVGE:    "cmovnl",
	CMOVNE:    "cmovnz",
	CMOVG:     "cmovnle",
	CMOVE:     "cmovz",
	LCALL:     "call far",
	LJMP:      "jmp far",
	LRET:      "ret far",
	ICEBP:     "int1",
	MOVSD_XMM: "movsd",
	XLATB:     "xlat",
}

	MOVW	b_len+16(FP), R2
	BEQ	R3, R4, samebytes
	SGTU	R1, R2, R7
	MOVW	R1, R8
	CMOVN	R7, R2, R8	// R8 is min(R1, R2)

	ADDU	R3, R8	// R3 is current byte in a, R8 is last byte in a to compare
loop:
	BEQ	R3, R8, samebytes

	MOVBU	(R3), R6
	ADDU	$1, R3
	MOVBU	(R4), R7
	ADDU	$1, R4
	BEQ	R6, R7 , loop

	SGTU	R6, R7, R8
	MOVW	$-1, R6
	CMOVZ	R8, R6, R8
	JMP	cmp_ret
samebytes:
	SGTU	R1, R2, R6
	SGTU	R2, R1, R7

	"FADDW",
	"FBLD",
	"FBSTP",
	"FCHS",
	"FCLEX",
	"FCMOVB",
	"FCMOVBE",
	"FCMOVCC",
	"FCMOVCS",
	"FCMOVE",
	"FCMOVEQ",
	"FCMOVHI",
	"FCMOVLS",
	"FCMOVNB",
	"FCMOVNBE",
	"FCMOVNE",
	"FCMOVNU",
	"FCMOVU",
	"FCMOVUN",
	"FCOMD",
	"FCOMDP",
	"FCOMDPP",
	"FCOMF",
	"FCOMFP",
	"FCOMI",
	"FCOMIP",
	"FCOML",
	"FCOMLP",
	"FCOMW",
	"FCOMWP",

}

func cmovload(a []int, i int, b bool) int {
	if b {
		i++
	}
	// See issue 26306
	// amd64:-"CMOVQNE"
	return a[i]
}

func cmovstore(a []int, i int, b bool) {
	if b {
		i++
	}
	// amd64:"CMOVQNE"
	a[i] = 7
}

var r0, r1, r2, r3, r4, r5 int

func cmovinc(cond bool, a, b, c int) {
	var x0, x1 int

	if cond {
		x0 = a
	} else {
		x0 = b + 1
	}

	"ADDF",
	"ADDU",
	"ADDW",
	"AND",
	"BEQ",
	"BFPF",
	"BFPT",
	"BGEZ",
	"BGEZAL",
	"BGTZ",
	"BLEZ",
	"BLTZ",
	"BLTZAL",
	"BNE",
	"BREAK",
	"CLO",
	"CLZ",
	"CMOVF",
	"CMOVN",
	"CMOVT",
	"CMOVZ",
	"CMPEQD",
	"CMPEQF",
	"CMPGED",
	"CMPGEF",
	"CMPGTD",
	"CMPGTF",
	"DIV",
	"DIVD",
	"DIVF",
	"DIVU",
	"DIVW",
	"GOK",
	"LL",
	"LLV",
	"LUI",
	"MADD",

	{i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO},
	{i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO},
	{i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG},
	{i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG},
	{i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG},
	{i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG},
	{i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG},
	{i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG},

(Rsh32Ux32 <t> x y) => (CMOVZ (SRL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
(Rsh32Ux16 <t> x y) => (CMOVZ (SRL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
(Rsh32Ux8 <t> x y)  => (CMOVZ (SRL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))

(Rsh16Ux32 <t> x y) => (CMOVZ (SRL <t> (ZeroExt16to32 x) y) (MOVWconst [0]) (SGTUconst [32] y))

	AMULLW
	AMULLD
	AMULHD
	AMULHDU
	AMLGR
	ASUB
	ASUBC
	ASUBV
	ASUBE
	ASUBW
	ANEG
	ANEGW

	// integer moves
	AMOVWBR
	AMOVB
	AMOVBZ
	AMOVH
	AMOVHBR
	AMOVHZ
	AMOVW
	AMOVWZ
	AMOVD
	AMOVDBR

	// conditional moves
	AMOVDEQ
	AMOVDGE
	AMOVDGT
	AMOVDLE
	AMOVDLT
	AMOVDNE
	ALOCR
	ALOCGR

	// find leftmost one
	AFLOGR

	//	}
	NOP	$4

	//
	// special
	//
	SYSCALL
	BREAK
	SYNC

	//
	// conditional move on zero/nonzero gp value
	//
	CMOVN	R1, R2, R3
	CMOVZ	R1, R2, R3

	//
	// conditional move on fp false/true
	//
	CMOVF	R1, R2
	CMOVT	R1, R2

	//
	// conditional traps
	//
	TEQ	$1, R1, R2
	TEQ	$1, R1


	//
	// other
	//
	CLO	R1, R2
	SQRTD	F0, F1

		switch t.Size() {
		case 1:
			if t.IsSigned() {
				return s390x.AMOVB
			} else {
				return s390x.AMOVBZ
			}
		case 2:
			if t.IsSigned() {
				return s390x.AMOVH
			} else {
				return s390x.AMOVHZ
			}
		case 4:
			if t.IsSigned() {
				return s390x.AMOVW
			} else {
				return s390x.AMOVWZ
			}
		case 8:
			return s390x.AMOVD
		}
	}
	panic("bad load type")
}