// Intel pseudonyms for our own renamings.
	PADDD	M2, M1 // PADDL M2, M1
	MOVDQ2Q	X1, M1 // MOVQ X1, M1
	MOVNTDQ	X1, (AX)	// MOVNTO X1, (AX)
	MOVOA	(AX), X1	// MOVO (AX), X1

// Tests for SP indexed addresses.
	MOVQ	foo(SP)(AX*1), BX		// 488b1c04
	MOVQ	foo+32(SP)(CX*2), DX		// 488b544c20
	MOVQ	foo+32323(SP)(R8*4), R9		// 4e8b8c84437e0000
	MOVL	foo(SP)(SI*8), DI		// 8b3cf4
	MOVL	foo+32(SP)(R10*1), R11		// 468b5c1420

	JMP	4(X5)					// 67804200

	// CALL and JMP to symbol are encoded as JAL (using LR or ZERO
	// respectively), with a R_RISCV_JAL relocation. The linker resolves
	// the real address and updates the immediate, using a trampoline in
	// the case where the address is not directly reachable.
	CALL	asmtest(SB)				// ef000000
	JMP	asmtest(SB)				// 6f000000

	// Branch pseudo-instructions
	BEQZ	X5, 2(PC)				// 63840200

	MOVL (AX)(Y0*1), AX             // ERROR "invalid instruction"
	// VSIB/VM is invalid without vector index.
	// TODO(quasilyte): improve error message (#21860).
	// "invalid VSIB address (missing vector index)"
	VPGATHERQQ Y2, (BP), Y1         // ERROR "invalid instruction"
	// AVX2GATHER mask/index/dest #UD cases.
	VPGATHERQQ Y2, (BP)(X2*2), Y2   // ERROR "mask, index, and destination registers should be distinct"