// Make sure we remove both inline marks in the following code.
// Both +5 and +6 should map to real instructions, which can
// be used as inline marks instead of explicit nops.
func f(x int) int {
	// amd64:-"XCHGL"
	x = g(x) + 5
	// amd64:-"XCHGL"
	x = g(x) + 6
	return x
}

func g(x int) int {
	return x >> 3

	MOVL	AX, ret_lo+12(FP)
	MOVL	DX, ret_hi+16(FP)
	RET

TEXT ·StorepNoWB(SB), NOSPLIT, $0-8
	MOVL	ptr+0(FP), BX
	MOVL	val+4(FP), AX
	XCHGL	AX, 0(BX)
	RET

TEXT ·Store(SB), NOSPLIT, $0-8
	MOVL	ptr+0(FP), BX
	MOVL	val+4(FP), AX
	XCHGL	AX, 0(BX)
	RET

TEXT ·StoreRel(SB), NOSPLIT, $0-8
	JMP	·Store(SB)

TEXT ·StoreReluintptr(SB), NOSPLIT, $0-8
	JMP	·Store(SB)

	JMP	·Xadd64(SB)

// uint32 Xchg(ptr *uint32, new uint32)
// Atomically:
//	old := *ptr;
//	*ptr = new;
//	return old;
TEXT ·Xchg(SB), NOSPLIT, $0-20
	MOVQ	ptr+0(FP), BX
	MOVL	new+8(FP), AX
	XCHGL	AX, 0(BX)
	MOVL	AX, ret+16(FP)
	RET

// uint64 Xchg64(ptr *uint64, new uint64)
// Atomically:
//	old := *ptr;
//	*ptr = new;
//	return old;
TEXT ·Xchg64(SB), NOSPLIT, $0-24
	MOVQ	ptr+0(FP), BX

	"WRFSBASEQ",
	"WRGSBASEL",
	"WRGSBASEQ",
	"WRMSR",
	"WRPKRU",
	"XABORT",
	"XACQUIRE",
	"XADDB",
	"XADDL",
	"XADDQ",
	"XADDW",
	"XBEGIN",
	"XCHGB",
	"XCHGL",
	"XCHGQ",
	"XCHGW",
	"XEND",
	"XGETBV",
	"XLAT",
	"XORB",
	"XORL",
	"XORPD",
	"XORPS",
	"XORQ",
	"XORW",
	"XRELEASE",
	"XRSTOR",
	"XRSTOR64",
	"XRSTORS",

	(XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem)
(XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) =>
	(XCHGL [off1+off2] {sym} val ptr mem)
(XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB =>
	(XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem)

// Merge ADDQconst into atomic adds.

	MOVL	machTimebaseInfo_numer(SP), SI
	MOVL	machTimebaseInfo_denom(SP), DI
	ADDQ	$(machTimebaseInfo__size+15)/16*16, SP

	MOVL	SI, timebase<>+machTimebaseInfo_numer(SB)
	MOVL	DI, AX
	XCHGL	AX, timebase<>+machTimebaseInfo_denom(SB) // atomic write

initialized:
	MOVL	SI, 8(BX)
	MOVL	DI, 12(BX)
	RET

TEXT runtime·walltime_trampoline(SB),NOSPLIT,$0
	MOVQ	DI, SI			// arg 2 timespec

	XCHGW R11, R11                          // 664587db
	XCHGL DX, (BX)                          // 8713
	XCHGL R11, (BX)                         // 44871b
	XCHGL DX, (R11)                         // 418713
	XCHGL R11, (R11)                        // 45871b
	XCHGL DX, DX                            // 87d2
	XCHGL R11, DX                           // 4487da
	XCHGL DX, R11                           // 4187d3

		{name: "XCHGB", argLength: 3, reg: gpstorexchg, asm: "XCHGB", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: "RdWr"},
		{name: "XCHGL", argLength: 3, reg: gpstorexchg, asm: "XCHGL", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, hasSideEffects: true, symEffect: "RdWr"},

	}
	return false
}
func rewriteValueAMD64_OpAMD64XCHGL(v *Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem)
	// cond: is32Bit(int64(off1)+int64(off2))
	// result: (XCHGL [off1+off2] {sym} val ptr mem)
	for {
		off1 := auxIntToInt32(v.AuxInt)
		sym := auxToSym(v.Aux)
		val := v_0
		if v_1.Op != OpAMD64ADDQconst {

			},
			outputs: []outputInfo{
				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "XCHGL",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            x86.AXCHGL,