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src/cmd/asm/internal/asm/testdata/s390x.s
KMCTR R2, R6, R4 // b92d6024 // vector add and sub instructions VAB V3, V4, V4 // e743400000f3 VAH V3, V4, V4 // e743400010f3 VAF V3, V4, V4 // e743400020f3 VAG V3, V4, V4 // e743400030f3 VAQ V3, V4, V4 // e743400040f3 VAB V1, V2 // e721200000f3 VAH V1, V2 // e721200010f3
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Nov 22 03:55:32 GMT 2023 - 21.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/operand_test.go
{"VS58", "VS58"}, {"VS59", "VS59"}, {"VS60", "VS60"}, {"VS61", "VS61"}, {"VS62", "VS62"}, {"VS63", "VS63"}, {"V0", "V0"}, {"V1", "V1"}, {"V2", "V2"}, {"V3", "V3"}, {"V4", "V4"}, {"V5", "V5"}, {"V6", "V6"}, {"V7", "V7"}, {"V8", "V8"}, {"V9", "V9"}, {"V10", "V10"}, {"V11", "V11"}, {"V12", "V12"}, {"V13", "V13"}, {"V14", "V14"}, {"V15", "V15"},
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 29 18:31:05 GMT 2023 - 23.9K bytes - Viewed (0) -
src/archive/zip/reader_test.go
dirEnts := []string{ "PK\x01\x02\n\x00\n\x00\x00\b\x00\x004\x9d3?\xaa\x1b\x06\xf0\x81\x02\x00\x00\x81\x02\x00\x00-\x00\x05\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00res/drawable-xhdpi-v4/ic_actionbar_accept.png\xfe\xca\x00\x00\x00", "PK\x01\x02\n\x00\n\x00\x00\b\x00\x004\x9d3?\x90K\x89\xc7t\n\x00\x00t\n\x00\x00\x0e\x00\x03\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xd1\x02\x00\x00resources.arsc\x00\x00\x00",
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Mar 27 18:23:49 GMT 2024 - 55.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/parse.go
} } // registerList parses an ARM or ARM64 register list expression, a list of // registers in []. There may be comma-separated ranges or individual // registers, as in [R1,R3-R5] or [V1.S4, V2.S4, V3.S4, V4.S4]. // For ARM, only R0 through R15 may appear. // For ARM64, V0 through V31 with arrangement may appear. // // For 386/AMD64 register list specifies 4VNNIW-style multi-source operand.
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src/cmd/asm/internal/asm/testdata/arm64error.s
VFMLS V1.H8, V12.H8, V3.H8 // ERROR "invalid arrangement" VFMLS V1.H4, V12.H4, V3.H4 // ERROR "invalid arrangement" VST1.P [V4.S4,V5.S4], 48(R1) // ERROR "invalid post-increment offset" VST1.P [V4.S4], 8(R1) // ERROR "invalid post-increment offset" VLD1.P 32(R1), [V8.S4, V9.S4, V10.S4] // ERROR "invalid post-increment offset"
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 08 03:28:17 GMT 2023 - 37.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
VLD1.P 1(R0), V4.B[15] // 041cdf4d VLD1.P 2(R0), V4.H[7] // 0458df4d VLD1.P 4(R0), V4.S[3] // 0490df4d VLD1.P 8(R0), V4.D[1] // 0484df4d VLD1.P (R0)(R1), V4.D[1] // 0484c14d VLD1 (R0), V4.D[1] // 0484404d
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 08 03:28:17 GMT 2023 - 94.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
AESE V31.B16, V29.B16 // fd4b284e AESIMC V12.B16, V27.B16 // 9b79284e AESMC V14.B16, V28.B16 // dc69284e VAND V4.B16, V4.B16, V9.B16 // 891c244e VCMEQ V24.S4, V13.S4, V12.S4 // ac8db86e VCNT V13.B8, V11.B8 // ab59200e
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Mon Jul 24 01:11:41 GMT 2023 - 43.9K bytes - Viewed (1) -
src/cmd/asm/internal/asm/testdata/ppc64.s
VCMPNEW V1, V2, V3 // 10611087 VCMPNEWCC V1, V2, V3 // 10611487 VPERM V1, V2, V3, V4 // 108110eb VPERMR V1, V2, V3, V4 // 108110fb VPERMXOR V1, V2, V3, V4 // 108110ed VBPERMQ V1, V2, V3 // 1061154c VBPERMD V1, V2, V3 // 106115cc VSEL V1, V2, V3, V4 // 108110ea VSPLTB $1, V1, V2 // 10410a0c VSPLTH $1, V1, V2 // 10410a4c
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Apr 24 15:53:25 GMT 2024 - 49K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64_p10.s
VEXTDDVLX V1, V2, R3, V4 // 108110de VEXTDDVRX V1, V2, R3, V4 // 108110df VEXTDUBVLX V1, V2, R3, V4 // 108110d8 VEXTDUBVRX V1, V2, R3, V4 // 108110d9 VEXTDUHVLX V1, V2, R3, V4 // 108110da VEXTDUHVRX V1, V2, R3, V4 // 108110db VEXTDUWVLX V1, V2, R3, V4 // 108110dc
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