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Results 1 - 6 of 6 for SHRWconst (0.18 sec)

  1. src/cmd/compile/internal/ssa/_gen/386Ops.go

    		{name: "SHRLconst", argLength: 1, reg: gp11, asm: "SHRL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> auxint, shift amount 0-31
    		{name: "SHRWconst", argLength: 1, reg: gp11, asm: "SHRW", aux: "Int16", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> auxint, shift amount 0-15
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 14 08:10:32 UTC 2023
    - 45.1K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/rewrite386.go

    		return true
    	}
    	return false
    }
    func rewriteValue386_Op386SHRW(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (SHRW x (MOVLconst [c]))
    	// cond: c&31 < 16
    	// result: (SHRWconst [int16(c&31)] x)
    	for {
    		x := v_0
    		if v_1.Op != Op386MOVLconst {
    			break
    		}
    		c := auxIntToInt32(v_1.AuxInt)
    		if !(c&31 < 16) {
    			break
    		}
    		v.reset(Op386SHRWconst)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Apr 21 21:05:46 UTC 2023
    - 262.4K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/AMD64Ops.go

    		{name: "SHRLconst", argLength: 1, reg: gp11, asm: "SHRL", aux: "Int8", resultInArg0: true, clobberFlags: true},
    		{name: "SHRWconst", argLength: 1, reg: gp11, asm: "SHRW", aux: "Int8", resultInArg0: true, clobberFlags: true},
    		{name: "SHRBconst", argLength: 1, reg: gp11, asm: "SHRB", aux: "Int8", resultInArg0: true, clobberFlags: true},
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Aug 04 16:40:24 UTC 2023
    - 98K bytes
    - Viewed (1)
  4. src/cmd/compile/internal/ssa/_gen/AMD64.rules

    (SHLL x (MOV(Q|L)const [c])) => (SHLLconst [int8(c&31)] x)
    
    (SHRQ x (MOV(Q|L)const [c])) => (SHRQconst [int8(c&63)] x)
    (SHRL x (MOV(Q|L)const [c])) => (SHRLconst [int8(c&31)] x)
    (SHRW x (MOV(Q|L)const [c])) && c&31 < 16 => (SHRWconst [int8(c&31)] x)
    (SHRW _ (MOV(Q|L)const [c])) && c&31 >= 16 => (MOVLconst [0])
    (SHRB x (MOV(Q|L)const [c])) && c&31 < 8 => (SHRBconst [int8(c&31)] x)
    (SHRB _ (MOV(Q|L)const [c])) && c&31 >= 8 => (MOVLconst [0])
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 93.9K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/rewriteAMD64.go

    	}
    	return false
    }
    func rewriteValueAMD64_OpAMD64SHRW(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (SHRW x (MOVQconst [c]))
    	// cond: c&31 < 16
    	// result: (SHRWconst [int8(c&31)] x)
    	for {
    		x := v_0
    		if v_1.Op != OpAMD64MOVQconst {
    			break
    		}
    		c := auxIntToInt64(v_1.AuxInt)
    		if !(c&31 < 16) {
    			break
    		}
    		v.reset(OpAMD64SHRWconst)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 712.7K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/opGen.go

    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 239}, // AX CX DX BX BP SI DI
    			},
    			outputs: []outputInfo{
    				{0, 239}, // AX CX DX BX BP SI DI
    			},
    		},
    	},
    	{
    		name:         "SHRWconst",
    		auxType:      auxInt16,
    		argLen:       1,
    		resultInArg0: true,
    		clobberFlags: true,
    		asm:          x86.ASHRW,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 239}, // AX CX DX BX BP SI DI
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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