FMAXNMD F20, F6, F16                       // d068741e
	//TODO VFMAXNMP V3.S2, F2                  // 62c8307e
	//TODO VFMAXNMP V25.S2, V4.S2, V2.S2       // 82c4392e
	//TODO VFMAXNMV V14.S4, F15                // cfc9306e
	//TODO VFMAXP V3.S2, F27                   // 7bf8307e
	//TODO VFMAXP V29.S2, V30.S2, V9.S2        // c9f73d2e
	//TODO VFMAXV V13.S4, F14                  // aef9306e

		for j := 0; j < 6; j++ {
			var tr *Reader
			var s1, s2 string

			switch j {
			case 0:
				tr = NewReader(&reader{strings.NewReader(v.input)})
				s1, s2 = "io.Reader", "auto"
			case 1:
				tr = NewReader(&reader{strings.NewReader(v.input)})
				s1, s2 = "io.Reader", "manual"
			case 2:
				tr = NewReader(&readSeeker{strings.NewReader(v.input)})
				s1, s2 = "io.ReadSeeker", "auto"
			case 3:

	VFMLA	V1.S4, V12.S2, V3.D2                             // ERROR "operand mismatch"
	VFMLA	V1.H4, V12.H4, V3.D2                             // ERROR "operand mismatch"
	VFMLS	V1.S2, V12.S2, V3.S4                             // ERROR "operand mismatch"
	VFMLS	V1.S2, V12.D2, V3.S4                             // ERROR "operand mismatch"

pkg debug/elf, const R_LARCH_SOP_NOT R_LARCH #46229
pkg debug/elf, const R_LARCH_SOP_POP_32_S_0_10_10_16_S2 = 45 #46229
pkg debug/elf, const R_LARCH_SOP_POP_32_S_0_10_10_16_S2 R_LARCH #46229
pkg debug/elf, const R_LARCH_SOP_POP_32_S_0_5_10_16_S2 = 44 #46229
pkg debug/elf, const R_LARCH_SOP_POP_32_S_0_5_10_16_S2 R_LARCH #46229
pkg debug/elf, const R_LARCH_SOP_POP_32_S_10_12 = 40 #46229

	register["A2"] = riscv.REG_A2
	register["A3"] = riscv.REG_A3
	register["A4"] = riscv.REG_A4
	register["A5"] = riscv.REG_A5
	register["A6"] = riscv.REG_A6
	register["A7"] = riscv.REG_A7
	register["S2"] = riscv.REG_S2
	register["S3"] = riscv.REG_S3
	register["S4"] = riscv.REG_S4
	register["S5"] = riscv.REG_S5
	register["S6"] = riscv.REG_S6
	register["S7"] = riscv.REG_S7
	register["S8"] = riscv.REG_S8

		case "H8":
			if isIndex {
				return errors.New("invalid register extension")
			}
			a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8H & 15) << 5)
		case "S2":
			if isIndex {
				return errors.New("invalid register extension")
			}
			a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2S & 15) << 5)
		case "S4":
			if isIndex {