Even so, Go provides a mechanism called GODEBUG to
reduce the impact such changes have on Go developers
using newer toolchains to compile old code.

A GODEBUG setting is a `key=value` pair
that controls the execution of certain parts of a Go program.
The environment variable `GODEBUG`
can hold a comma-separated list of these settings.
For example, if a Go program is running in an environment that contains

		if p.arch.InFamily(sys.ARM, sys.ARM64) {
			// Special form
			// ARM: destination register pair (R1, R2).
			// ARM64: register pair (R1, R2) for LDP/STP.
			if prefix != 0 || scale != 0 {
				p.errorf("illegal address mode for register pair")
				return
			}
			a.Type = obj.TYPE_REGREG
			a.Offset = int64(r2)
			// Nothing may follow
			return
		}

<code>[R0,g,R12-R15]</code>: For multi-register instructions, the set comprising
<code>R0</code>, <code>g</code>, and <code>R12</code> through <code>R15</code> inclusive.
</li>

<li>
<code>(R5, R6)</code>: Destination register pair.
</li>

</ul>

<h3 id="arm64">ARM64</h3>

<p>
<code>R18</code> is the "platform register", reserved on the Apple platform.
To prevent accidental misuse, the register is named <code>R18_PLATFORM</code>.

pkg debug/macho, const ARM_RELOC_HALF_SECTDIFF RelocTypeARM
pkg debug/macho, const ARM_RELOC_LOCAL_SECTDIFF = 3
pkg debug/macho, const ARM_RELOC_LOCAL_SECTDIFF RelocTypeARM
pkg debug/macho, const ARM_RELOC_PAIR = 1
pkg debug/macho, const ARM_RELOC_PAIR RelocTypeARM
pkg debug/macho, const ARM_RELOC_PB_LA_PTR = 4
pkg debug/macho, const ARM_RELOC_PB_LA_PTR RelocTypeARM
pkg debug/macho, const ARM_RELOC_SECTDIFF = 2

		return true
	}
	return false
}

// IsARM64CASP reports whether the op (as defined by an arm64.A*
// constant) is one of the CASP-like instructions, and its 2nd
// destination is a register pair that require special handling.
func IsARM64CASP(op obj.As) bool {
	switch op {
	case arm64.ACASPD, arm64.ACASPW:
		return true
	}
	return false
}

and <i>w'</i> happens before <i>r</i>.
That is, each read must observe a value written by a preceding or concurrent write.
</p>

<p>
Additionally, observation of acausal and “out of thin air” writes is disallowed.
</p>

<p>
Reads of memory locations larger than a single machine word
are encouraged but not required to meet the same semantics
as word-sized memory locations,

	CASPD	(R2, R3), (R2), (R9, R10)                        // ERROR "destination register pair must start from even register"
	CASPD	(R2, R4), (R2), (R8, R9)                         // ERROR "source register pair must be contiguous"
	CASPD	(R2, R3), (R2), (R8, R10)                        // ERROR "destination register pair must be contiguous"

				// both 1st operand and 3rd operand are (Rs, Rs+1) register pair.
				// And the register pair must be contiguous.
				if (a[0].Type != obj.TYPE_REGREG) || (a[2].Type != obj.TYPE_REGREG) {
					p.errorf("invalid addressing modes for 1st or 3rd operand to %s instruction, must be register pair", op)
					return
				}
				// For ARM64 CASP-like instructions, its 2nd destination operand is register pair(Rt, Rt+1) that can