}

// IsLoong64MUL reports whether the op (as defined by an loong64.A* constant) is
// one of the MUL/DIV/REM instructions that require special handling.
func IsLoong64MUL(op obj.As) bool {
	switch op {
	case loong64.AMUL, loong64.AMULU, loong64.AMULV, loong64.AMULVU,
		loong64.ADIV, loong64.ADIVU, loong64.ADIVV, loong64.ADIVVU,
		loong64.AREM, loong64.AREMU, loong64.AREMV, loong64.AREMVU:
		return true
	}
	return false
}

WANG Xuerui <******@****.***> 1679394224 +0800

		fi
	done

	return 0
}

assert_is_supported_arch() {
	case "${ARCH}" in
	x86_64 | amd64 | aarch64 | ppc64le | arm* | s390x | loong64 | loongarch64)
		return
		;;
	*)
		echo "Arch '${ARCH}' is not supported. Supported Arch: [x86_64, amd64, aarch64, ppc64le, arm*, s390x, loong64, loongarch64]"
		exit 1
		;;
	esac
}

assert_is_supported_os() {
	case "${KNAME}" in

	for i := loong64.REG_R0; i <= loong64.REG_R31; i++ {
		register[obj.Rconv(i)] = int16(i)
	}
	for i := loong64.REG_F0; i <= loong64.REG_F31; i++ {
		register[obj.Rconv(i)] = int16(i)
	}
	for i := loong64.REG_FCSR0; i <= loong64.REG_FCSR31; i++ {
		register[obj.Rconv(i)] = int16(i)
	}
	for i := loong64.REG_FCC0; i <= loong64.REG_FCC31; i++ {
		register[obj.Rconv(i)] = int16(i)
	}

	testEndToEnd(t, "mips", "mips")
	testEndToEnd(t, "mips64", "mips64")
}

func TestLOONG64Encoder(t *testing.T) {
	testEndToEnd(t, "loong64", "loong64enc1")
	testEndToEnd(t, "loong64", "loong64enc2")
	testEndToEnd(t, "loong64", "loong64enc3")
	testEndToEnd(t, "loong64", "loong64")
}

func TestPPC64EndToEnd(t *testing.T) {
	defer func(old int) { buildcfg.GOPPC64 = old }(buildcfg.GOPPC64)

			if arch.IsMIPSCMP(op) || arch.IsMIPSMUL(op) {
				prog.From = a[0]
				prog.Reg = p.getRegister(prog, op, &a[1])
				break
			}
		} else if p.arch.Family == sys.Loong64 {
			if arch.IsLoong64RDTIME(op) {
				// The Loong64 RDTIME family of instructions is a bit special,
				// in that both its register operands are outputs
				prog.To = a[0]
				if a[1].Type != obj.TYPE_REG {

	MOVV	R4, FCSR3		// 83c01401
	MOVV	FCSR3, R4		// 64c81401
	MOVV	F4, FCC0		// 80d01401
	MOVV	FCC0, F4		// 04d41401
	MOVV    FCC0, R4		// 04dc1401
	MOVV    R4, FCC0		// 80d81401

	// Loong64 atomic memory access instructions
	AMSWAPB		R14, (R13), R12 // ac395c38
	AMSWAPH		R14, (R13), R12 // acb95c38
	AMSWAPW		R14, (R13), R12 // ac396038
	AMSWAPV		R14, (R13), R12 // acb96038

}

func TestMIPS64OperandParser(t *testing.T) {
	parser := newParser("mips64")
	testOperandParser(t, parser, mips64OperandTests)
}

func TestLOONG64OperandParser(t *testing.T) {
	parser := newParser("loong64")
	testOperandParser(t, parser, loong64OperandTests)
}

func TestS390XOperandParser(t *testing.T) {
	parser := newParser("s390x")
	testOperandParser(t, parser, s390xOperandTests)
}

to a specified boundary by padding with no-op instructions.
</p>

<p>
It is currently supported on arm64, amd64, ppc64, loong64 and riscv64.

For example, the start of the <code>MOVD</code> instruction below is aligned to 32 bytes:
<pre>
PCALIGN $32
MOVD $2, R0
</pre>
</p>

		if gomips == "hardfloat" {
			return []string{"-mabi=32", "-mfp32", "-mhard-float", "-mno-odd-spreg"}
		} else if gomips == "softfloat" {
			return []string{"-mabi=32", "-msoft-float"}
		}
	case "loong64":
		return []string{"-mabi=lp64d"}
	}
	return nil
}

func gccTmp() string {
	return *objDir + "_cgo_.o"
}

// gccCmd returns the gcc command line to use for compiling