BFXU	$40, $4, R2, R3    // ERROR "wrong width or LSB"
	BFXU	$-40, $4, R2       // ERROR "wrong width or LSB"
	BFX	$-2, $4, R2, R3    // ERROR "wrong width or LSB"
	BFXU	$4, R2, R5, R2     // ERROR "missing or wrong LSB"
	BFXU	$4, R2, R5         // ERROR "missing or wrong LSB"
	BFC	$12, $8, R2, R3    // ERROR "illegal combination"
	MOVB	R0>>8, R2          // ERROR "illegal shift"
	MOVH	R0<<16, R2         // ERROR "illegal shift"

	TLBI	ALLE3OS, ZR                                      // ERROR "extraneous register at operand 2"
	TLBI	VAE1IS                                           // ERROR "missing register at operand 2"
	TLBI	RVALE3                                           // ERROR "missing register at operand 2"
	DC	PLDL1KEEP                                        // ERROR "illegal argument"
	DC	VMALLE1IS                                        // ERROR "illegal argument"

	MOVL (AX)(Y0*1), AX             // ERROR "invalid instruction"
	// VSIB/VM is invalid without vector index.
	// TODO(quasilyte): improve error message (#21860).
	// "invalid VSIB address (missing vector index)"
	VPGATHERQQ Y2, (BP), Y1         // ERROR "invalid instruction"
	// AVX2GATHER mask/index/dest #UD cases.
	VPGATHERQQ Y2, (BP)(X2*2), Y2   // ERROR "mask, index, and destination registers should be distinct"