VLUXEI8V	(X10), V2, V1, V3		// ERROR "invalid vector mask register"
	VSUXEI8V	V3, V2, V1, (X10)		// ERROR "invalid vector mask register"
	VLOXEI8V	(X10), V2, V1, V3		// ERROR "invalid vector mask register"
	VSOXEI8V	V3, V2, V1, (X10)		// ERROR "invalid vector mask register"
	VLSEG2E8V	(X10), V1, V3			// ERROR "invalid vector mask register"
	VLSEG2E8FFV	(X10), V1, V3			// ERROR "invalid vector mask register"

  std::vector<std::string> tensor_id_data;
};

struct TF_ImportGraphDefResults {
  std::vector<TF_Output> return_tensors;
  std::vector<TF_Operation*> return_nodes;
  std::vector<const char*> missing_unused_key_names;
  std::vector<int> missing_unused_key_indexes;

  // Backing memory for missing_unused_key_names values.
  std::vector<std::string> missing_unused_key_names_data;
};

                           const string& op_name) {
  std::vector<int64_t> input_ids(inputs.size());
  std::vector<tensorflow::DataType> input_dtypes(inputs.size());
  for (int i = 0; i < inputs.size(); i++) {
    input_ids[i] = ToId(inputs[i]);
    input_dtypes[i] = inputs[i]->DataType();
  }
  std::vector<TapeTensor> tape_tensors;
  tape_tensors.reserve(outputs.size());
  for (auto t : outputs) {

	// 31.11.15: Vector Integer Merge Instructions
	VMERGEVVM	V1, V2, V0, V3			// d781205c
	VMERGEVXM	X10, V2, V0, V3			// d741255c
	VMERGEVIM	$15, V2, V0, V3			// d7b1275c

	// 31.11.16: Vector Integer Move Instructions
	VMVVV		V2, V3				// d701015e
	VMVVX		X10, V3				// d741055e
	VMVVI		$15, V3				// d7b1075e

	// 31.12.1: Vector Single-Width Saturating Add and Subtract

    std::vector<TF_Output> out;
    for (auto op : ops) {
      out.push_back({op, 0});
    }
    return out;
  }

  void Define(int num_opers, const std::vector<TF_Operation*>& opers,
              const std::vector<TF_Operation*>& inputs,
              const std::vector<TF_Operation*>& outputs,
              const std::vector<std::string>& output_names,
              bool expect_failure = false) {

  }

  // Checks the expected result of shape inference for the given `op`.
  void CheckOutputShapes(
      TFE_Op* op,
      const std::vector<absl::optional<std::vector<int64_t>>>& input_shapes_vec,
      const std::vector<TF_Tensor*>& input_tensors,
      const absl::optional<std::vector<int64_t>>& expected_shape) {
    // Create input_shapes.
    TF_ShapeAndTypeList* input_shapes =

		}
	}
	if opd, ok := riscv64SpecialOperand[name]; ok {
		return opd
	}
	return riscv.SPOP_END
}

// RISCV64ValidateVectorType reports whether the given configuration is a
// valid vector type.
func RISCV64ValidateVectorType(vsew, vlmul, vtail, vmask int64) error {
	_, err := riscv.EncodeVectorType(vsew, vlmul, vtail, vmask)
	return err

    EXPECT_TRUE(found);
    TF_DeleteBuffer(op_list_buffer);
  }
}

void TestEncodeDecode(int line, const std::vector<std::string>& data) {
  const int64_t n = data.size();
  absl::Status status;
  for (const std::vector<int64_t>& dims :
       std::vector<std::vector<int64_t>>{{n}, {1, n}, {n, 1}, {n / 2, 2}}) {
    // Create C++ Tensor
    Tensor src(tensorflow::DT_STRING, TensorShape(dims));

    : reader_(nullptr),
      v2_reader_(nullptr),
      var_to_shape_map_(nullptr),
      var_to_data_type_map_(nullptr) {
  // Depending on whether this is a V2 ckpt, initializes "reader_" or
  // "v2_reader_".
  std::vector<string> v2_path;
  if (Env::Default()->GetMatchingPaths(MetaFilename(filename), &v2_path).ok() &&
      !v2_path.empty()) {
    v2_reader_.reset(
        new BundleReader(Env::Default(), filename /* prefix to a V2 ckpt */));

		return 0, errors.New("invalid register for shift operation")
	}
	return int64(reg&31)<<16 | int64(op)<<22 | int64(uint16(count)), nil
}

// ARM64RegisterArrangement constructs an ARM64 vector register arrangement.
func ARM64RegisterArrangement(reg int16, name, arng string) (int64, error) {
	var curQ, curSize uint16
	if name[0] != 'V' {
		return 0, errors.New("expect V0 through V31; found: " + name)
	}