VFWCVTXUFV	X10, V3				// ERROR "expected vector register in vs2 position"
	VFWCVTXFV	X10, V3				// ERROR "expected vector register in vs2 position"
	VFWCVTRTZXUFV	X10, V3				// ERROR "expected vector register in vs2 position"
	VFWCVTRTZXFV	X10, V3				// ERROR "expected vector register in vs2 position"
	VFWCVTFXUV	X10, V3				// ERROR "expected vector register in vs2 position"
	VFWCVTFXV	X10, V3				// ERROR "expected vector register in vs2 position"

	VLUXEI8V	(X10), V2, V1, V3		// ERROR "invalid vector mask register"
	VSUXEI8V	V3, V2, V1, (X10)		// ERROR "invalid vector mask register"
	VLOXEI8V	(X10), V2, V1, V3		// ERROR "invalid vector mask register"
	VSOXEI8V	V3, V2, V1, (X10)		// ERROR "invalid vector mask register"
	VLSEG2E8V	(X10), V1, V3			// ERROR "invalid vector mask register"
	VLSEG2E8FFV	(X10), V1, V3			// ERROR "invalid vector mask register"

  std::vector<std::string> tensor_id_data;
};

struct TF_ImportGraphDefResults {
  std::vector<TF_Output> return_tensors;
  std::vector<TF_Operation*> return_nodes;
  std::vector<const char*> missing_unused_key_names;
  std::vector<int> missing_unused_key_indexes;

  // Backing memory for missing_unused_key_names values.
  std::vector<std::string> missing_unused_key_names_data;
};

                           const string& op_name) {
  std::vector<int64_t> input_ids(inputs.size());
  std::vector<tensorflow::DataType> input_dtypes(inputs.size());
  for (int i = 0; i < inputs.size(); i++) {
    input_ids[i] = ToId(inputs[i]);
    input_dtypes[i] = inputs[i]->DataType();
  }
  std::vector<TapeTensor> tape_tensors;
  tape_tensors.reserve(outputs.size());
  for (auto t : outputs) {

	// 31.11.15: Vector Integer Merge Instructions
	VMERGEVVM	V1, V2, V0, V3			// d781205c
	VMERGEVXM	X10, V2, V0, V3			// d741255c
	VMERGEVIM	$15, V2, V0, V3			// d7b1275c

	// 31.11.16: Vector Integer Move Instructions
	VMVVV		V2, V3				// d701015e
	VMVVX		X10, V3				// d741055e
	VMVVI		$15, V3				// d7b1075e

	// 31.12.1: Vector Single-Width Saturating Add and Subtract

    std::vector<TF_Output> out;
    for (auto op : ops) {
      out.push_back({op, 0});
    }
    return out;
  }

  void Define(int num_opers, const std::vector<TF_Operation*>& opers,
              const std::vector<TF_Operation*>& inputs,
              const std::vector<TF_Operation*>& outputs,
              const std::vector<std::string>& output_names,
              bool expect_failure = false) {

  }

  // Checks the expected result of shape inference for the given `op`.
  void CheckOutputShapes(
      TFE_Op* op,
      const std::vector<absl::optional<std::vector<int64_t>>>& input_shapes_vec,
      const std::vector<TF_Tensor*>& input_tensors,
      const absl::optional<std::vector<int64_t>>& expected_shape) {
    // Create input_shapes.
    TF_ShapeAndTypeList* input_shapes =

	VMOVQ		V3.W[1], V7.W4  // 67e4f772
	VMOVQ		V4.V[0], V6.V2  // 86f0f772

	// Move vector register to vector register.
	VMOVQ		V1, V9		// 29002d73
	VMOVQ		V2, V8		// 48002d73
	XVMOVQ		X3, X7		// 67002d77
	XVMOVQ		X4, X6		// 86002d77

	// Load data from memory and broadcast to each element of a vector register: VMOVQ    offset(Rj), <Vd>.<T>
	VMOVQ		(R4), V0.B16	// 80008030
	VMOVQ		1(R4), V0.B16	// 80048030

    } else {
      TFE_OpAddInput(op, input, s);
    }
    if (TF_GetCode(s) != TF_OK) return;
  }
  std::vector<TFE_TensorHandle*> op_outputs(*num_outputs);
  TFE_Execute(op, op_outputs.data(), num_outputs, s);
  TFE_DeleteOp(op);
  if (TF_GetCode(s) != TF_OK) return;
  std::vector<TFE_TensorHandle*> unwrapped_outputs;
  unwrapped_outputs.reserve(op_outputs.size());
  for (auto* handle : op_outputs) {

		}
	}
	if opd, ok := riscv64SpecialOperand[name]; ok {
		return opd
	}
	return riscv.SPOP_END
}

// RISCV64ValidateVectorType reports whether the given configuration is a
// valid vector type.
func RISCV64ValidateVectorType(vsew, vlmul, vtail, vmask int64) error {
	_, err := riscv.EncodeVectorType(vsew, vlmul, vtail, vmask)
	return err