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  2. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/riscv64validation.s 

    	VSOXEI8V	V3, V2, (V1)			// ERROR "expected integer register in rs1 position"
	VSOXEI8V	V3, X11, V0, (X10)		// ERROR "expected vector register in vs2 position"
	VLSEG2E8V	(X10), X10			// ERROR "expected vector register in vd position"
	VLSEG2E8V	(V1), V3			// ERROR "expected integer register in rs1 position"
	VLSEG2E8FFV	(X10), X10			// ERROR "expected vector register in vd position"
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Thu Nov 13 12:17:37 GMT 2025
    - 42.1K bytes
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