(x47 + i263) << 2 + 1 // var z = new(P256Element).Set(e) var t0 = new(P256Element) var t1 = new(P256Element) z.Square(x) z.Mul(x, z) z.Square(z) z.Mul(x, z) t0.Square(z) for s := 1; s < 3; s++ { t0.Square(t0) } t0.Mul(z, t0) t1.Square(t0) for s := 1; s < 6; s++ { t1.Square(t1) } t0.Mul(t0, t1) for s := 0; s < 3; s++ { t0.Square(t0) } z.Mul(z, t0) t0.Square(z) t0.Mul(x, t0) t1.Square(t0) for s := 1; s < 16; s++ { t1.Square(t1) } t0.Mul(t0, t1) for s := 0; s < 15; s++ { t0.Square(t0) } z.Mul(z, t0)...

     * is to avoid unnecessary stalls in situations like this: A RateLimiter of 1qps, and 4 threads,
     * all calling acquire() at these moments:
     *
     * T0 at 0 seconds
     * T1 at 1.05 seconds
     * T2 at 2 seconds
     * T3 at 3 seconds
     *
     * Due to the slight delay of T1, T2 would have to sleep till 2.05 seconds, and T3 would also

	// General registers with ABI names.
	register["ZERO"] = riscv.REG_ZERO
	register["RA"] = riscv.REG_RA
	register["SP"] = riscv.REG_SP
	register["GP"] = riscv.REG_GP
	register["TP"] = riscv.REG_TP
	register["T0"] = riscv.REG_T0
	register["T1"] = riscv.REG_T1
	register["T2"] = riscv.REG_T2
	register["S0"] = riscv.REG_S0
	register["S1"] = riscv.REG_S1
	register["A0"] = riscv.REG_A0
	register["A1"] = riscv.REG_A1

        .body("B")
        .build(),
    )

    // A cache miss writes the cache.
    val t0 = System.currentTimeMillis()
    val response1 = get(server.url("/a"))
    assertThat(response1.body.string()).isEqualTo("A")
    assertThat(response1.header("Allow")).isNull()
    assertThat((response1.receivedResponseAtMillis - t0).toDouble()).isCloseTo(0.0, 250.0)

    // A conditional cache hit updates the cache.

</p>

<pre>
type T0 struct {
	x int
}

func (*T0) M0()

type T1 struct {
	y int
}

func (T1) M1()

type T2 struct {
	z int
	T1
	*T0
}

func (*T2) M2()

type Q *T2

var t T2     // with t.T0 != nil
var p *T2    // with p != nil and (*p).T0 != nil
var q Q = p
</pre>

<p>