val b1: Int
      get() =
        when {
          codepointDelta < 0 -> 0x40 or (absoluteDelta shr 14)
          codepointDelta > 0 -> 0x50 or (absoluteDelta shr 14)
          else -> error("Unexpected codepointDelta of 0")
        }

    val b2: Int
      get() = absoluteDelta shr 7 and 0x7f

    val b3: Int
      get() = absoluteDelta and 0x7f

    companion object {

    val sectionOffset = rangesBuffer.size.toInt() / 4

    // Section prefix.
    sectionIndexBuffer.writeByte(section and 0x1fc000 shr 14)
    sectionIndexBuffer.writeByte((section and 0x3f80) shr 7)

    // Section index.
    sectionIndexBuffer.writeByte((sectionOffset and 0x3f80) shr 7)
    sectionIndexBuffer.writeByte(sectionOffset and 0x7f)

    // Ranges.
    for (range in sectionMappedRanges) {

      val lengthByteCount = (lengthBitCount + 7) / 8
      sink.writeByte(0b1000_0000 or lengthByteCount)
      for (shift in (lengthByteCount - 1) * 8 downTo 0 step 8) {
        sink.writeByte((length shr shift).toInt())
      }
    }

    // Write the payload.
    sink.writeAll(content)
  }

  /**
   * Execute [block] with a new namespace for type hints. Type hints from the enclosing type are no

(MOVBQZX x) && zeroUpper56Bits(x,3)...

	// amd64:"SHRQ.*,.*,"
	shr := x>>s | y<<ŝ
	// amd64:"SHLQ.*,.*,"
	shl := x<<s | y>>ŝ
	return shr, shl
}

func checkShiftToMask(u []uint64, s []int64) {
	// amd64:-"SHR",-"SHL","ANDQ"
	u[0] = u[0] >> 5 << 5
	// amd64:-"SAR",-"SHL","ANDQ"
	s[0] = s[0] >> 5 << 5
	// amd64:-"SHR",-"SHL","ANDQ"
	u[1] = u[1] << 5 >> 5

      accumulator = (accumulator shl codeBitCount) or code.toLong()
      accumulatorBitCount += codeBitCount

      while (accumulatorBitCount >= 8) {
        accumulatorBitCount -= 8
        sink.writeByte((accumulator shr accumulatorBitCount).toInt())
      }
    }

    if (accumulatorBitCount > 0) {
      accumulator = accumulator shl (8 - accumulatorBitCount)
      accumulator = accumulator or (0xffL ushr accumulatorBitCount)

func store_le64(b []byte, x uint64) {
	// amd64:`MOVQ\s.*\(.*\)$`,-`SHR.`
	// arm64:`MOVD`,-`MOV[WBH]`
	// ppc64le:`MOVD\s`,-`MOV[BHW]\s`
	// ppc64:`MOVDBR`,-MOVB\s`
	// s390x:`MOVDBR\s.*\(.*\)$`
	binary.LittleEndian.PutUint64(b, x)
}

func store_le64_idx(b []byte, x uint64, idx int) {
	// amd64:`MOVQ\s.*\(.*\)\(.*\*1\)$`,-`SHR.`
	// arm64:`MOVD\sR[0-9]+,\s\(R[0-9]+\)\(R[0-9]+\)`,-`MOV[BHW]`

    val result = mutableListOf<InetAddress>()

    val buf = Buffer()
    buf.write(byteString)
    buf.readShort() // query id

    val flags = buf.readShort().toInt() and 0xffff
    require(flags shr 15 != 0) { "not a response" }

    val responseCode = flags and 0xf

    if (responseCode == NXDOMAIN) {
      throw UnknownHostException("$hostname: NXDOMAIN")
    } else if (responseCode == SERVFAIL) {

	})
	b.Run("ShlSame", func(b *testing.B) {
		for i := 0; i < b.N; i++ {
			x.shl(x, 0)
		}
	})

	b.Run("Shr", func(b *testing.B) {
		for i := 0; i < b.N; i++ {
			var z nat
			z.shr(x, 0)
		}
	})
	b.Run("ShrSame", func(b *testing.B) {
		for i := 0; i < b.N; i++ {
			x.shr(x, 0)
		}
	})
}

type modWTest struct {
	in       string
	dividend string
	out      string
}

	SLL	$8, X7; \
	OR	X5, X7, X5; \
	OR	X5, X8, X5; \
	MOV	X5, (index*8)(X19)

// Wt = SIGMA1(Wt-2) + Wt-7 + SIGMA0(Wt-15) + Wt-16; for 16 <= t <= 79
//   SIGMA0(x) = ROTR(1,x) XOR ROTR(8,x) XOR SHR(7,x)
//   SIGMA1(x) = ROTR(19,x) XOR ROTR(61,x) XOR SHR(6,x)
#define MSGSCHEDULE1(index) \
	MOV	(((index-2)&0xf)*8)(X19), X5; \
	MOV	(((index-15)&0xf)*8)(X19), X6; \
	MOV	(((index-7)&0xf)*8)(X19), X9; \
	MOV	(((index-16)&0xf)*8)(X19), X21; \