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Results 1 - 9 of 9 for mtvsrws (0.14 sec)

  1. src/cmd/internal/obj/ppc64/anames.go

    	"STXVB16X",
    	"STXVX",
    	"LXSDX",
    	"STXSDX",
    	"LXSIWAX",
    	"LXSIWZX",
    	"STXSIWX",
    	"MFVSRD",
    	"MFFPRD",
    	"MFVRD",
    	"MFVSRWZ",
    	"MFVSRLD",
    	"MTVSRD",
    	"MTFPRD",
    	"MTVRD",
    	"MTVSRWA",
    	"MTVSRWZ",
    	"MTVSRDD",
    	"MTVSRWS",
    	"XXLAND",
    	"XXLANDC",
    	"XXLEQV",
    	"XXLNAND",
    	"XXLOR",
    	"XXLORC",
    	"XXLNOR",
    	"XXLORQ",
    	"XXLXOR",
    	"XXSEL",
    	"XXMRGHW",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 6.7K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/ppc64.s

    	MFVSRLD V31,R4                  // 7fe40267
    	MFVSRWZ VS33,R4                 // 7c2400e7
    	MFVSRWZ V1,R4                   // 7c2400e7
    	MTVSRD R3, VS1                  // 7c230166
    	MTVSRDD R3, R4, VS1             // 7c232366
    	MTVSRDD R3, R4, VS33            // 7c232367
    	MTVSRDD R3, R4, V1              // 7c232367
    	MTVRD R3, V13                   // 7da30167
    	MTVSRWA R4, VS31                // 7fe401a6
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/ppc64/asm9.go

    		case AMFVSRD: /* mfvsrd, mfvsrwz (and extended mnemonics), mfvsrld */
    			opset(AMFFPRD, r0)
    			opset(AMFVRD, r0)
    			opset(AMFVSRWZ, r0)
    			opset(AMFVSRLD, r0)
    
    		case AMTVSRD: /* mtvsrd, mtvsrwa, mtvsrwz (and extended mnemonics), mtvsrdd, mtvsrws */
    			opset(AMTFPRD, r0)
    			opset(AMTVRD, r0)
    			opset(AMTVSRWA, r0)
    			opset(AMTVSRWZ, r0)
    			opset(AMTVSRWS, r0)
    
    		case AXXLAND:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 13:55:28 UTC 2024
    - 156.1K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/ppc64/a.out.go

    	ASTXVX
    	ALXSDX
    	ASTXSDX
    	ALXSIWAX
    	ALXSIWZX
    	ASTXSIWX
    	AMFVSRD
    	AMFFPRD
    	AMFVRD
    	AMFVSRWZ
    	AMFVSRLD
    	AMTVSRD
    	AMTFPRD
    	AMTVRD
    	AMTVSRWA
    	AMTVSRWZ
    	AMTVSRDD
    	AMTVSRWS
    	AXXLAND
    	AXXLANDC
    	AXXLEQV
    	AXXLNAND
    	AXXLOR
    	AXXLORC
    	AXXLNOR
    	AXXLORQ
    	AXXLXOR
    	AXXSEL
    	AXXMRGHW
    	AXXMRGLW
    	AXXSPLTW
    	AXXSPLTIB
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 16K bytes
    - Viewed (0)
  5. test/codegen/math.go

    	// mips64/hardfloat:"MOVW\tF.*, R.*"
    	return math.Float32bits(f32+1) + 1
    }
    
    func toFloat64(u64 uint64) float64 {
    	// amd64:"MOVQ\t[^X].*, X.*"
    	// arm64:"FMOVD\tR.*, F.*"
    	// ppc64x:"MTVSRD"
    	// mips64/hardfloat:"MOVV\tR.*, F.*"
    	return math.Float64frombits(u64+1) + 1
    }
    
    func toFloat32(u32 uint32) float32 {
    	// amd64:"MOVL\t[^X].*, X.*"
    	// arm64:"FMOVS\tR.*, F.*"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Apr 04 15:24:29 UTC 2024
    - 6.2K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/PPC64.rules

    (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr x _)) => (MFVSRD x)
    (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr x _)) => (MTVSRD x)
    
    (FMOVDstore [off] {sym} ptr (MTVSRD x) mem) => (MOVDstore [off] {sym} ptr x mem)
    (MOVDstore [off] {sym} ptr (MFVSRD x) mem) => (FMOVDstore [off] {sym} ptr x mem)
    
    (MTVSRD (MOVDconst [c])) && !math.IsNaN(math.Float64frombits(uint64(c))) => (FMOVDconst [math.Float64frombits(uint64(c))])
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 53.2K bytes
    - Viewed (0)
  7. src/math/big/arith_ppc64x.s

    	CMP     R8, R4
    	BGE     loopexit        // Already at end?
    
    	// vectorize if len(z) is >=3, else jump to scalar loop
    	CMP     R4, $3
    	BLT     scalar
    	MTVSRD  R9, VS38        // s
    	VSPLTB  $7, V6, V4
    	MTVSRD  R5, VS39        // ŝ
    	VSPLTB  $7, V7, V2
    	ADD     $-2, R4, R16
    	PCALIGN $16
    loopback:
    	ADD     $-1, R8, R10
    	SLD     $3, R10
    	LXVD2X  (R6)(R10), VS32 // load x[i-1], x[i]
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 18:17:17 UTC 2024
    - 16.8K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/PPC64Ops.go

    		{name: "MFVSRD", argLength: 1, reg: fpgp, asm: "MFVSRD", typ: "Int64"},   // move 64 bits of F register into G register
    		{name: "MTVSRD", argLength: 1, reg: gpfp, asm: "MTVSRD", typ: "Float64"}, // move 64 bits of G register into F register
    
    		{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true},                           // arg0&arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 43.8K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/opGen.go

    			},
    			outputs: []outputInfo{
    				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
    			},
    		},
    	},
    	{
    		name:   "MTVSRD",
    		argLen: 1,
    		asm:    ppc64.AMTVSRD,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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