(MOVQstore dst (MOVQload src mem) mem))

(Move [32] dst src mem) =>
	(Move [16]
		(OffPtr <dst.Type> dst [16])
		(OffPtr <src.Type> src [16])
		(Move [16] dst src mem))

(Move [48] dst src mem) && config.useSSE =>
	(Move [32]
		(OffPtr <dst.Type> dst [16])
		(OffPtr <src.Type> src [16])
		(Move [16] dst src mem))

(Move [64] dst src mem) && config.useSSE =>
	(Move [32]
		(OffPtr <dst.Type> dst [32])

	// amd64:`MOVWLZX\s\(.*\),`,-`MOVB`,-`OR`
	// ppc64le:`MOVHZ\s`,-`MOVBZ`
	// arm64:`MOVHU\s\(R[0-9]+\),`,-`MOVB`
	// s390x:`MOVHBR\s\(.*\),`
	// ppc64:`MOVHBR\s`,-`MOVBZ`
	return binary.LittleEndian.Uint16(b)
}

func load_le16_idx(b []byte, idx int) uint16 {
	// amd64:`MOVWLZX\s\(.*\),`,-`MOVB`,-`OR`
	// ppc64le:`MOVHZ\s`,-`MOVBZ`
	// ppc64:`MOVHBR\s`,-`MOVBZ`
	// arm64:`MOVHU\s\(R[0-9]+\)\(R[0-9]+\),`,-`MOVB`

	MOVQ	$masks<>(SB), AX
	MOVQ	$shifts<>(SB), BX
	ORQ	BX, AX
	TESTQ	$15, AX
	SETEQ	ret+0(FP)
	RET

// these are arguments to pshufb. They move data down from
// the high bytes of the register to the low bytes of the register.
// index is how many bytes to move.
DATA shifts<>+0x00(SB)/8, $0x0000000000000000
DATA shifts<>+0x08(SB)/8, $0x0000000000000000
DATA shifts<>+0x10(SB)/8, $0xffffffffffffff0f

	MOVWU	R4, result+16(FP)	// 64608029
	MOVV	R4, result+16(FP)	// 6460c029
	MOVB	R4, result+16(FP)	// 64600029
	MOVBU	R4, result+16(FP)	// 64600029
	MOVWL	R4, result+16(FP)	// 6460002f
	MOVVL	R4, result+16(FP)	// 6460802f
	MOVW	R4, 1(R5)		// a4048029
	MOVWU	R4, 1(R5)		// a4048029
	MOVV	R4, 1(R5)		// a404c029
	MOVB	R4, 1(R5)		// a4040029
	MOVBU	R4, 1(R5)		// a4040029
	MOVWL	R4, 1(R5)		// a404002f
	MOVVL	R4, 1(R5)		// a404802f

	RET

TEXT ·Store8(SB), NOSPLIT, $0-9
	MOVV	ptr+0(FP), R1
	MOVB	val+8(FP), R2
	SYNC
	MOVB	R2, 0(R1)
	SYNC
	RET

TEXT ·Store64(SB), NOSPLIT, $0-16
	MOVV	ptr+0(FP), R1
	MOVV	val+8(FP), R2
	SYNC
	MOVV	R2, 0(R1)
	SYNC
	RET

// void	Or8(byte volatile*, byte);
TEXT ·Or8(SB), NOSPLIT, $0-9
	MOVV	ptr+0(FP), R1
	MOVBU	val+8(FP), R2

// func And8(ptr *uint8, val uint8)
TEXT ·And8(SB), NOSPLIT, $0-9
	MOV	ptr+0(FP), A0
	MOVBU	val+8(FP), A1
	AND	$3, A0, A2
	AND	$-4, A0
	SLL	$3, A2
	XOR	$255, A1
	SLL	A2, A1
	XOR	$-1, A1
	AMOANDW A1, (A0), ZERO
	RET

// func Or8(ptr *uint8, val uint8)
TEXT ·Or8(SB), NOSPLIT, $0-9
	MOV	ptr+0(FP), A0
	MOVBU	val+8(FP), A1
	AND	$3, A0, A2
	AND	$-4, A0
	SLL	$3, A2
	SLL	A2, A1

	MOV	$1234, 8(SP)			// ERROR "constant load must target register"
	MOVB	$1, X5				// ERROR "unsupported constant load"
	MOVH	$1, X5				// ERROR "unsupported constant load"
	MOVW	$1, X5				// ERROR "unsupported constant load"
	MOVF	$1, X5				// ERROR "unsupported constant load"
	MOVBU	X5, (X6)			// ERROR "unsupported unsigned store"
	MOVHU	X5, (X6)			// ERROR "unsupported unsigned store"

	"LU32ID",
	"LU52ID",
	"PCALAU12I",
	"PCADDU12I",
	"JIRL",
	"BGE",
	"BLT",
	"BLTU",
	"BGEU",
	"DIV",
	"DIVD",
	"DIVF",
	"DIVU",
	"DIVW",
	"LL",
	"LLV",
	"LUI",
	"MOVB",
	"MOVBU",
	"MOVD",
	"MOVDF",
	"MOVDW",
	"MOVF",
	"MOVFD",
	"MOVFW",
	"MOVH",
	"MOVHU",
	"MOVW",
	"MOVWD",
	"MOVWF",
	"MOVWL",
	"MOVWR",
	"MUL",
	"MULD",
	"MULF",
	"MULU",

	MOVHZ (R3), R5                  // a0a30000
	MOVB 1(R3), R4                  // 888300017c840774
	MOVB (R3)(R4), R5               // 7ca418ae7ca50774
	MOVB (R3)(R0), R5               // 7ca018ae7ca50774
	MOVB (R3), R5                   // 88a300007ca50774
	MOVBZ 1(R3), R4                 // 88830001
	MOVBZ (R3)(R4), R5              // 7ca418ae
	MOVBZ (R3)(R0), R5              // 7ca018ae
	MOVBZ (R3), R5                  // 88a30000

TEXT ·Cas(SB), NOSPLIT, $0-17
	MOVD	ptr+0(FP), R0
	MOVW	old+8(FP), R1
	MOVW	new+12(FP), R2
#ifndef GOARM64_LSE
	MOVBU	internal∕cpu·ARM64+const_offsetARM64HasATOMICS(SB), R4
	CBZ 	R4, load_store_loop
#endif
	MOVD	R1, R3
	CASALW	R3, (R0), R2
	CMP 	R1, R3
	CSET	EQ, R0
	MOVB	R0, ret+16(FP)
	RET
#ifndef GOARM64_LSE
load_store_loop:
	LDAXRW	(R0), R3
	CMPW	R1, R3
	BNE	ok
	STLXRW	R2, (R0), R3