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Results 1 - 10 of 10 for icbt (0.11 sec)
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src/cmd/internal/obj/ppc64/anames.go
"SUBECC", "SUBEV", "SUBEVCC", "SUBZE", "SUBZECC", "SUBZEVCC", "SUBZEV", "SYNC", "XOR", "XORCC", "XORIS", "DCBF", "DCBI", "DCBST", "DCBT", "DCBTST", "DCBZ", "EIEIO", "ICBI", "ISYNC", "PTESYNC", "TLBIE", "TLBIEL", "TLBSYNC", "TW", "SYSCALL", "WORD", "RFCI", "FCPSGN", "FCPSGNCC", "FRES", "FRESCC", "FRIM",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/math/big/arith_ppc64x.s
ADDC R20, R4, R6 // R6 = x[i] + c CMP R11, $0 // If z_len was 1, we are done MOVD R6, 0(R10) // z[i] BEQ final // We will read 4 elements per iteration SRDCC $2, R11, R9 // R9 = z_len/4 DCBT (R8) MOVD R9, CTR // Set up the loop counter BEQ tail // If R9 = 0, we can't use the loop PCALIGN $16 loop: MOVD 8(R8), R20 // R20 = x[i] MOVD 16(R8), R21 // R21 = x[i+1]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 16.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
// Prefetch instructions (TH specified using aux field) // For DCBT Ra,Rb,TH, A value of TH indicates: // 0, hint this cache line will be used soon. (PrefetchCache) // 16, hint this cache line will not be used for long. (PrefetchCacheStreamed) // See ISA 3.0 Book II 4.3.2 for more detail. https://openpower.foundation/specifications/isa/ (PrefetchCache ptr mem) => (DCBT ptr mem [0]) (PrefetchCacheStreamed ptr mem) => (DCBT ptr mem [16])
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
// Prefetch instruction // Do prefetch of address generated with arg0 and arg1 with option aux. arg0=addr,arg1=memory, aux=option. {name: "DCBT", argLength: 2, aux: "Int64", reg: prefreg, asm: "DCBT", hasSideEffects: true}, // Store bytes in the reverse endian order of the arch into arg0. // These are indexed stores with no offset field in the instruction so the auxint fields are not used.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
guava/src/com/google/thirdparty/publicsuffix/PublicSuffixPatterns.java
e???s&citsigol?e&civres?r??krow?serp!xe??tnega??t&farcr&ia?otor??hgil&f?orcim??liubemoh?n&atlusnoc?e&duts?m&esuma?n&iatretne?revog??piuqe????olip?ropria?si&lanruoj?tneics???w&erc?ohs??y&cnegreme?dobper?tefas????rref?z??p!.&a&aa?ca?pc??dem?ecartsnd.icb,gne?korgn,r&ab?uj??s&nduolc,rahc21,?t&acova?cca?hcer??wal?ysrab,???s!.&em?gro?hcs,moc?syevrus,ten?ude?vog???t!.&0x,116,ayo,gro?lim?moc?nayn,sulpnpv,t&cennockciuq.tcerid,en??ude?v&dr,og???o&hp?m?v?yk??tol?ua??v&iv?lov??xas?ykot??p&a&ehc?g?m?s??eej?g...
Registered: Wed Jun 12 16:38:11 UTC 2024 - Last Modified: Thu Mar 21 21:04:43 UTC 2024 - 72.4K bytes - Viewed (0) -
android/guava/src/com/google/thirdparty/publicsuffix/PublicSuffixPatterns.java
e???s&citsigol?e&civres?r??krow?serp!xe??tnega??t&farcr&ia?otor??hgil&f?orcim??liubemoh?n&atlusnoc?e&duts?m&esuma?n&iatretne?revog??piuqe????olip?ropria?si&lanruoj?tneics???w&erc?ohs??y&cnegreme?dobper?tefas????rref?z??p!.&a&aa?ca?pc??dem?ecartsnd.icb,gne?korgn,r&ab?uj??s&nduolc,rahc21,?t&acova?cca?hcer??wal?ysrab,???s!.&em?gro?hcs,moc?syevrus,ten?ude?vog???t!.&0x,116,ayo,gro?lim?moc?nayn,sulpnpv,t&cennockciuq.tcerid,en??ude?v&dr,og???o&hp?m?v?yk??tol?ua??v&iv?lov??xas?ykot??p&a&ehc?g?m?s??eej?g...
Registered: Wed Jun 12 16:38:11 UTC 2024 - Last Modified: Thu Mar 21 21:04:43 UTC 2024 - 72.4K bytes - Viewed (1) -
src/cmd/internal/obj/ppc64/asm9.go
} o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11 case 43: /* data cache instructions: op (Ra+[Rb]), [th|l] */ /* TH field for dcbt/dcbtst: */ /* 0 = Block access - program will soon access EA. */ /* 8-15 = Stream access - sequence of access (data stream). See section 4.3.2 of the ISA for details. */
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 13:55:28 UTC 2024 - 156.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
v.AddArg(v0) return true } } func rewriteValuePPC64_OpPrefetchCache(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (PrefetchCache ptr mem) // result: (DCBT ptr mem [0]) for { ptr := v_0 mem := v_1 v.reset(OpPPC64DCBT) v.AuxInt = int64ToAuxInt(0) v.AddArg2(ptr, mem) return true } }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "DCBT", auxType: auxInt64, argLen: 2, hasSideEffects: true, asm: ppc64.ADCBT, reg: regInfo{ inputs: []inputInfo{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)