BCDADDCC:       "bcdadd.",
	BCDSUBCC:       "bcdsub.",
	BCTAR:          "bctar",
	BCTARL:         "bctarl",
	CLRBHRB:        "clrbhrb",
	FMRGEW:         "fmrgew",
	FMRGOW:         "fmrgow",
	ICBT:           "icbt",
	LQARX:          "lqarx",
	LXSIWAX:        "lxsiwax",
	LXSIWZX:        "lxsiwzx",
	LXSSPX:         "lxsspx",
	MFBHRBE:        "mfbhrbe",
	MFVSRD:         "mfvsrd",
	MFVSRWZ:        "mfvsrwz",

	"SUBECC",
	"SUBEV",
	"SUBEVCC",
	"SUBZE",
	"SUBZECC",
	"SUBZEVCC",
	"SUBZEV",
	"SYNC",
	"XOR",
	"XORCC",
	"XORIS",
	"DCBF",
	"DCBI",
	"DCBST",
	"DCBT",
	"DCBTST",
	"DCBZ",
	"EIEIO",
	"ICBI",
	"ISYNC",
	"PTESYNC",
	"TLBIE",
	"TLBIEL",
	"TLBSYNC",
	"TW",
	"SYSCALL",
	"WORD",
	"RFCI",
	"FCPSGN",
	"FCPSGNCC",
	"FRES",
	"FRESCC",
	"FRIM",

// license that can be found in the LICENSE file.

#include "textflag.h"

// func syncIcache(p uintptr)
TEXT main·syncIcache(SB), NOSPLIT|NOFRAME, $0-0
	SYNC
	MOVD (R3), R3
	ICBI (R3)
	ISYNC

// license that can be found in the LICENSE file.

#include "textflag.h"

// func syncIcache(p uintptr)
TEXT main·syncIcache(SB), NOSPLIT|NOFRAME, $0-0
	SYNC
	MOVD (R3), R3
	ICBI (R3)
	ISYNC

	case LXV:
		return op + " " + args[1] + "," + args[0]

	case LXVL, LXVLL:
		return op + " " + args[1] + "," + args[2] + "," + args[0]

	case DCBT, DCBTST, DCBZ, DCBST, ICBI:
		if args[0] == "0" || args[0] == "R0" {
			return op + " (" + args[1] + ")"
		}
		return op + " (" + args[1] + ")(" + args[0] + ")"

	// branch instructions needs additional handling
	case BCLR:

	DCBZ (R3)(R0)                   // 7c001fec
	DCBZ (R3)                       // 7c001fec
	DCBT (R3)(R4)                   // 7c041a2c
	DCBT (R3)(R0)                   // 7c001a2c
	DCBT (R3)                       // 7c001a2c
	ICBI (R3)(R4)                   // 7c041fac
	ICBI (R3)(R0)                   // 7c001fac
	ICBI (R3)                       // 7c001fac

	// float constants
	FMOVD $(0.0), F1                // f0210cd0

TEXT cmpbody<>(SB),NOSPLIT|NOFRAME,$0-0
start:
	CMP	R9,$16,CR0
	CMP	R9,$32,CR1
	CMP	R9,$64,CR2
	MOVD	$16,R10
	BLT	cmp8
	BLT	CR1,cmp16
	BLT	CR2,cmp32

cmp64:	// >= 64B
	DCBT	(R5)		// optimize for size>=64
	DCBT	(R6)		// cache hint

	SRD	$6,R9,R14	// There is at least one iteration.
	MOVD	R14,CTR
	ANDCC   $63,R9,R9
	CMP	R9,$16,CR1	// Do setup for tail check early on.
	CMP	R9,$32,CR2
	CMP	R9,$48,CR3

	SRDCC	$3, DWORDS, OCTWORDS	// 64 byte chunks?
	MOVD	$16, IDX16
	BEQ	lt64gt8			// < 64 bytes

	// Prepare for moves of 64 bytes at a time.

forward64setup:
	DCBTST	(TGT)			// prepare data cache
	DCBT	(SRC)
	MOVD	OCTWORDS, CTR		// Number of 64 byte chunks
	MOVD	$32, IDX32
	MOVD	$48, IDX48
	PCALIGN	$16

forward64:
	LXVD2X	(R0)(SRC), VS32		// load 64 bytes
	LXVD2X	(IDX16)(SRC), VS33
	LXVD2X	(IDX32)(SRC), VS34

	ADDC  R20, R4, R6	// R6 = x[i] + c
	CMP   R11, $0		// If z_len was 1, we are done
	MOVD  R6, 0(R10)	// z[i]
	BEQ   final

	// We will read 4 elements per iteration
	SRDCC $2, R11, R9	// R9 = z_len/4
	DCBT  (R8)
	MOVD  R9, CTR		// Set up the loop counter
	BEQ   tail		// If R9 = 0, we can't use the loop
	PCALIGN $16

loop:
	MOVD  8(R8), R20	// R20 = x[i]
	MOVD  16(R8), R21	// R21 = x[i+1]

// Prefetch instructions (TH specified using aux field)
// For DCBT Ra,Rb,TH, A value of TH indicates:
//     0, hint this cache line will be used soon. (PrefetchCache)
//     16, hint this cache line will not be used for long. (PrefetchCacheStreamed)
// See ISA 3.0 Book II 4.3.2 for more detail. https://openpower.foundation/specifications/isa/
(PrefetchCache ptr mem)          => (DCBT ptr mem [0])
(PrefetchCacheStreamed ptr mem)  => (DCBT ptr mem [16])