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src/cmd/asm/internal/asm/testdata/riscv64validation.s
VREDXORVS X10, V2, V3 // ERROR "expected vector register in vs1 position" VWREDSUMUVS X10, V2, V3 // ERROR "expected vector register in vs1 position" VWREDSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position" VFREDOSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position" VFREDUSUMVS X10, V2, V3 // ERROR "expected vector register in vs1 position"
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Nov 13 12:17:37 GMT 2025 - 42.1K bytes - Click Count (0) -
lib/fips140/v1.26.0.zip
CR2, keysLoaded; \ ADD $64, R16; \ ADD $64, R17; \ LXVD2X (blk_key)(R16), VS13; \ LXVD2X (blk_key)(R17), VS14; \ CMP key_len, $14; \ BEQ keysLoaded; \ MOVD R0,0(R0); \ keysLoaded: // Encrypt 1 (vin) with first 9 // keys from VS1 - VS9. #define VCIPHER_1X9_KEYS(vin) \ XXLOR VS1, VS1, V23; \ XXLOR VS2, VS2, V24; \ XXLOR VS3, VS3, V25; \ XXLOR VS4, VS4, V26; \ XXLOR VS5, VS5, V27; \ VCIPHER vin, V23, vin; \ VCIPHER vin, V24, vin; \ VCIPHER vin, V25, vin; \ VCIPHER vin, V26, vin; \ VCIPHER vin, V27, vin;...
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Thu Jan 08 17:58:32 GMT 2026 - 660.3K bytes - Click Count (0)