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  2. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/riscv64validation.s 

    	VREDXORVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
	VWREDSUMUVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
	VWREDSUMVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
	VFREDOSUMVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
	VFREDUSUMVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed May 21 14:19:19 UTC 2025
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