VLE8V		(X10), V0, V3			// 87010500
	VLE16V		(X10), V3			// 87510502
	VLE16V		(X10), V0, V3			// 87510500
	VLE32V		(X10), V3			// 87610502
	VLE32V		(X10), V0, V3			// 87610500
	VLE64V		(X10), V3			// 87710502
	VLE64V		(X10), V0, V3			// 87710500
	VSE8V		V3, (X10)			// a7010502
	VSE8V		V3, V0, (X10)			// a7010500
	VSE16V		V3, (X10)			// a7510502
	VSE16V		V3, V0, (X10)			// a7510500

      entryItr.remove();
    }
    assertTrue(getMap().isEmpty());
  }

  public void testContainsEntryWithIncomparableKey() {
    try {
      assertFalse(getMap().entrySet().contains(mapEntry(IncomparableType.INSTANCE, v0())));
    } catch (ClassCastException acceptable) {
      // allowed by the spec
    }
  }

  public void testContainsEntryWithIncomparableValue() {
    try {

      entryItr.remove();
    }
    assertTrue(getMap().isEmpty());
  }

  public void testContainsEntryWithIncomparableKey() {
    try {
      assertFalse(getMap().entrySet().contains(mapEntry(IncomparableType.INSTANCE, v0())));
    } catch (ClassCastException acceptable) {
      // allowed by the spec
    }
  }

  public void testContainsEntryWithIncomparableValue() {
    try {

	VADCVVM		V1, V2, V3			// ERROR "invalid vector mask register"
	VADCVVM		V1, V2, V0, V0			// ERROR "invalid destination register V0"
	VADCVXM		X10, V2, V4, V3			// ERROR "invalid vector mask register"
	VADCVXM		X10, V2, V3			// ERROR "invalid vector mask register"
	VADCVXM		X10, V2, V0, V0			// ERROR "invalid destination register V0"
	VADCVIM		$15, V2, V1, V3			// ERROR "invalid vector mask register"

	UMULL R19, R22, R19                        // d37eb39b
	UXTBW R2, R6                               // 461c0053
	UXTHW R7, R20                              // f43c0053
	VCNT V0.B8, V0.B8                          // 0058200e
	VCNT V0.B16, V0.B16                        // 0058204e
	WFE                                        // 5f2003d5
	WFI                                        // 7f2003d5

	VCMEQ	V1.H4, V2.H4, V3.H4             // 438c612e
	VORR	V5.B16, V4.B16, V3.B16          // 831ca54e
	VADD	V16.S4, V5.S4, V9.S4            // a984b04e
	VEOR	V0.B16, V1.B16, V0.B16          // 201c206e
	VADDV	V0.S4, V0                       // 00b8b14e
	VMOVI	$82, V0.B16                     // 40e6024f
	VUADDLV	V6.B16, V6                      // c638306e
	VADD	V1, V2, V3                      // 4384e15e

[V13.B16, V14.B16, V15.B16] AESE V5.B16, V0.B16 AESMC V0.B16, V0.B16 AESE V6.B16, V0.B16 AESMC V0.B16, V0.B16 AESE V7.B16, V0.B16 AESMC V0.B16, V0.B16 AESE V8.B16, V0.B16 AESMC V0.B16, V0.B16 AESE V9.B16, V0.B16 AESMC V0.B16, V0.B16 AESE V10.B16, V0.B16 AESMC V0.B16, V0.B16 AESE V11.B16, V0.B16 AESMC V0.B16, V0.B16 AESE V12.B16, V0.B16 AESMC V0.B16, V0.B16 AESE V13.B16, V0.B16 AESMC V0.B16, V0.B16 AESE V14.B16, V0.B16 VEOR V0.B16, V15.B16, V0.B16 VST1 [V0.B16], (R11) RET // func decryptBlockAsm(nr...

	VUXTL2	V20.B8, V21.H8                                   // ERROR "operand mismatch"
	VUXTL	V3.D2, V4.B8                                     // ERROR "operand mismatch"
	VUZP1	V0.B8, V30.B8, V1.B16                            // ERROR "operand mismatch"
	VUZP2	V0.Q1, V30.Q1, V1.Q1                             // ERROR "invalid arrangement"
	VUSHLL	$0, V30.D2, V30.H8                               // ERROR "operand mismatch"

func ARM64RegisterArrangement(reg int16, name, arng string) (int64, error) {
	var curQ, curSize uint16
	if name[0] != 'V' {
		return 0, errors.New("expect V0 through V31; found: " + name)
	}
	if reg < 0 {
		return 0, errors.New("invalid register number: " + name)
	}
	switch arng {
	case "B8":
		curSize = 0
		curQ = 0
	case "B16":
		curSize = 0

	XVMOVQ		X3, X7		// 67002d77
	XVMOVQ		X4, X6		// 86002d77

	// Load data from memory and broadcast to each element of a vector register: VMOVQ    offset(Rj), <Vd>.<T>
	VMOVQ		(R4), V0.B16	// 80008030
	VMOVQ		1(R4), V0.B16	// 80048030
	VMOVQ		-3(R4), V0.B16	// 80f4bf30
	VMOVQ		(R4), V1.H8	// 81004030
	VMOVQ		2(R4), V1.H8	// 81044030
	VMOVQ		-6(R4), V1.H8	// 81f45f30
	VMOVQ		(R4), V2.W4	// 82002030
	VMOVQ		8(R4), V2.W4	// 82082030