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Results 1 - 3 of 3 for S0 (0.09 seconds)

  1. src/cmd/asm/internal/arch/arch.go

    	register["SP"] = riscv.REG_SP
    	register["GP"] = riscv.REG_GP
    	register["TP"] = riscv.REG_TP
    	register["T0"] = riscv.REG_T0
    	register["T1"] = riscv.REG_T1
    	register["T2"] = riscv.REG_T2
    	register["S0"] = riscv.REG_S0
    	register["S1"] = riscv.REG_S1
    	register["A0"] = riscv.REG_A0
    	register["A1"] = riscv.REG_A1
    	register["A2"] = riscv.REG_A2
    	register["A3"] = riscv.REG_A3
    	register["A4"] = riscv.REG_A4
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Fri Mar 20 17:02:17 GMT 2026
    - 22K bytes
    - Click Count (0)
  2. lib/fips140/v1.26.0.zip

    $1, S1; \ VADDUWM xi, h, h; \ VSHASIGMAW $0, a, $1, S0; \ VADDUWM FUNC, h, h; \ VXOR b, a, FUNC; \ VADDUWM S1, h, h; \ VSEL b, c, FUNC, FUNC; \ VADDUWM KI, g, g; \ VADDUWM h, d, d; \ VADDUWM FUNC, S0, S0; \ LVX (TBL)(idx), KI; \ VADDUWM S0, h, h #define SHA256ROUND1(a, b, c, d, e, f, g, h, xi, xj, xj_1, xj_9, xj_14, idx) \ VSHASIGMAW $0, xj_1, $0, s0; \ VSEL g, f, e, FUNC; \ VSHASIGMAW $15, e, $1, S1; \ VADDUWM xi, h, h; \ VSHASIGMAW $0, a, $1, S0; \ VSHASIGMAW $15, xj_14, $0, s1; \ VADDUWM FUNC, h,...
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Thu Jan 08 17:58:32 GMT 2026
    - 660.3K bytes
    - Click Count (0)
  3. doc/go_spec.html

    Otherwise, <code>append</code> re-uses the underlying array.
    </p>
    
    <pre>
    s0 := []int{0, 0}
    s1 := append(s0, 2)                // append a single element     s1 is []int{0, 0, 2}
    s2 := append(s1, 3, 5, 7)          // append multiple elements    s2 is []int{0, 0, 2, 3, 5, 7}
    s3 := append(s2, s0...)            // append a slice              s3 is []int{0, 0, 2, 3, 5, 7, 0, 0}
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Wed Apr 01 23:39:18 GMT 2026
    - 287.8K bytes
    - Click Count (1)
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