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Results 1 - 5 of 5 for RLL (0.03 sec)
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src/crypto/md5/md5block_s390x.s
MOVWBR 0(R6), R8 MOVWZ R5, R9 #define ROUND1(a, b, c, d, index, const, shift) \ XOR c, R9; \ ADD $const, a; \ ADD R8, a; \ MOVWBR (index*4)(R6), R8; \ AND b, R9; \ XOR d, R9; \ ADD R9, a; \ RLL $shift, a; \ MOVWZ c, R9; \ ADD b, a ROUND1(R2,R3,R4,R5, 1,0xd76aa478, 7); ROUND1(R5,R2,R3,R4, 2,0xe8c7b756,12); ROUND1(R4,R5,R2,R3, 3,0x242070db,17); ROUND1(R3,R4,R5,R2, 4,0xc1bdceee,22);
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 4.4K bytes - Viewed (0) -
test/codegen/rotate.go
a += x<<7 | x>>25 // amd64:`ROLL\t[$]8` // arm:"MOVW\tR\\d+@>24" // arm64:"RORW\t[$]24" // s390x:"RLL\t[$]8" // ppc64x:"ROTLW\t[$]8" // loong64: "ROTR\t[$]24" // riscv64: "RORIW\t[$]24" a += x<<8 + x>>24 // amd64:"ROLL\t[$]9" // arm:"MOVW\tR\\d+@>23" // arm64:"RORW\t[$]23" // s390x:"RLL\t[$]9" // ppc64x:"ROTLW\t[$]9" // loong64: "ROTR\t[$]23" // riscv64: "RORIW\t[$]23" a += x<<9 ^ x>>23
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 6K bytes - Viewed (0) -
test/codegen/mathbits.go
// wasm:"I64Rotl" return bits.RotateLeft64(n, 37) } func RotateLeft32(n uint32) uint32 { // amd64:"ROLL" 386:"ROLL" // arm:`MOVW\tR[0-9]+@>23` // arm64:"RORW" // ppc64x:"ROTLW" // s390x:"RLL" // wasm:"I32Rotl" return bits.RotateLeft32(n, 9) } func RotateLeft16(n uint16, s int) uint16 { // amd64:"ROLW" 386:"ROLW" // arm64:"RORW",-"CSEL" return bits.RotateLeft16(n, s) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 18:51:17 UTC 2024 - 19.6K bytes - Viewed (0) -
src/internal/runtime/atomic/atomic_s390x.s
ORW $~0xff, R4 // R4 = uint32(v) | 0xffffff00 MOVD $(3<<3), R5 RXSBG $59, $60, $3, R3, R5 // R5 = 24 - ((addr % 4) * 8) = ((addr & 3) << 3) ^ (3 << 3) ANDW $~3, R3 // R3 = floor(addr, 4) = addr &^ 3 RLL R5, R4, R4 // R4 = rotl(R4, R5) LAN R4, R6, 0(R3) // R6 = *R3; *R3 &= R4; (atomic) RET // func Or(addr *uint32, v uint32) TEXT ·Or(SB), NOSPLIT, $0-12 MOVD ptr+0(FP), R3 MOVW val+8(FP), R4
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 7.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, outputs: []outputInfo{ {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 }, }, }, { name: "RLL", argLen: 2, asm: s390x.ARLL, reg: regInfo{ inputs: []inputInfo{ {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)