ADD	$74565, R4, R5			// 5e020014de178d0385781000
	ADD	$4097, R4, R5  			// 3e000014de07800385781000
	ADDW	$74565, R4, R5			// 5e020014de178d0385781000
	ADDW	$4097, R4, R5  			// 3e000014de07800385781000
	ADDV	$74565, R4, R5			// 5e020014de178d0385f81000
	ADDV	$4097, R4, R5 			// 3e000014de07800385f81000
	AND	$74565, R4, R5			// 5e020014de178d0385f81400
	AND	$4097, R4, R5			// 3e000014de07800385f81400

	ADDS	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	ADDSW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUB	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUBW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"

	ADDW	$65536, R4, R5		// 1e02001485781000
	ADDW	$4096, R4, R5		// 3e00001485781000
	ADDW	$65536, R4		// 1e02001484781000
	ADDW	$4096, R4		// 3e00001484781000
	ADDV	$65536, R4, R5		// 1e02001485f81000
	ADDV	$4096, R4, R5		// 3e00001485f81000
	ADDV	$65536, R4		// 1e02001484f81000
	ADDV	$4096, R4		// 3e00001484f81000
	AND	$65536, R4, R5		// 1e02001485f81400
	AND	$4096, R4, R5		// 3e00001485f81400

	SWPLD	R5, (RSP), R7                        // e78365f8
	SWPLW	R5, (R6), R7                         // c78065b8
	SWPLW	R5, (RSP), R7                        // e78365b8
	SWPLH	R5, (R6), R7                         // c7806578
	SWPLH	R5, (RSP), R7                        // e7836578
	SWPLB	R5, (R6), R7                         // c7806538
	SWPLB	R5, (RSP), R7                        // e7836538

	SUB	R4, R5			// a5101100
	SUBW	R4, R5			// a5101100
	SUBV	R4, R5			// a5901100
	ADD	R4, R5			// a5101000
	ADDW	R4, R5			// a5101000
	ADDV	R4, R5			// a5901000
	AND	R4, R5			// a5901400
	NEGW	R4, R5			// 05101100
	NEGV	R4, R5			// 05901100
	SLL	R4, R5			// a5101700
	SLL	R4, R5, R6		// a6101700
	SRL	R4, R5			// a5901700
	SRL	R4, R5, R6	 	// a6901700
	SRA	R4, R5			// a5101800
	SRA	R4, R5, R6	 	// a6101800
	ROTR	R4, R5			// a5101b00

	CMNW $(2<<12), R5                          // CMNW $8192, R5                // bf084031
	CMN $(8<<12), R12                          // CMN $32768, R12               // 9f2140b1
	CMN R6->0, R3                              // 7f0086ab
	CMN R6, R3                                 // 7f0006ab
	CMNW R30, R5                               // bf001e2b
	CMNW $2, R5                                // bf080031

R6-R12. ADD $112, R5 // Load xk[28:35] and cipher LXVD2X (R0+R5), V1 LXVD2X (R6+R5), V2 VCIPHER V0, V1, V0 VCIPHER V0, V2, V0 // Load xk[36:43] and cipher LXVD2X (R7+R5), V1 LXVD2X (R8+R5), V2 BEQ CR1, Ldec_tail // Key size 10? VCIPHER V0, V1, V0 VCIPHER V0, V2, V0 // Load xk[44:51] and cipher LXVD2X (R9+R5), V1 LXVD2X (R10+R5), V2 BEQ CR2, Ldec_tail // Key size 12? VCIPHER V0, V1, V0 VCIPHER V0, V2, V0 // Load xk[52:59] and cipher LXVD2X (R11+R5), V1 LXVD2X (R12+R5), V2 BNE CR3, Linvalid_key_len // Not...

<p>
Load- and store-multiple instructions operate on a range of registers.
The range of registers is specified by a start register and an end register.
For example, <code>LMG</code> <code>(R9),</code> <code>R5,</code> <code>R7</code> would load
<code>R5</code>, <code>R6</code> and <code>R7</code> with the 64-bit values at
<code>0(R9)</code>, <code>8(R9)</code> and <code>16(R9)</code> respectively.
</p>

<p>

    public void test_mixedReadingsLengths() {
        String[] text = { "word1", "word2", "word3" };
        String[][] readings = { { "r1", "r2", "r3" }, // 3 readings
                { "r4" }, // 1 reading
                { "r5", "r6" } // 2 readings
        };

        SuggestItem item = new SuggestItem(text, readings, null, 0L, 0L, 1.0f, null, null, null, SuggestItem.Kind.QUERY);

        assertEquals(3, item.getReadings()[0].length);

		a.Scale = int16(scale)
	}
}

// registerList parses an ARM or ARM64 register list expression, a list of
// registers in []. There may be comma-separated ranges or individual
// registers, as in [R1,R3-R5] or [V1.S4, V2.S4, V3.S4, V4.S4].
// For ARM, only R0 through R15 may appear.
// For ARM64, V0 through V31 with arrangement may appear.
//
// For 386/AMD64 register list specifies 4VNNIW-style multi-source operand.