AMANDV		R14, (R13), R12 // acb96238
	AMORW		R14, (R13), R12 // ac396338
	AMORV		R14, (R13), R12 // acb96338
	AMXORW		R14, (R13), R12 // ac396438
	AMXORV		R14, (R13), R12 // acb96438
	AMMAXW		R14, (R13), R12 // ac396538
	AMMAXV		R14, (R13), R12 // acb96538
	AMMINW		R14, (R13), R12 // ac396638
	AMMINV		R14, (R13), R12 // acb96638
	AMMAXWU		R14, (R13), R12 // ac396738
	AMMAXVU		R14, (R13), R12 // acb96738

	ADD	R2.SXTX<<1, RSP, RSP            // ffe7228b
	ADD	ZR.SXTX<<1, R2, R3              // 43e43f8b
	ADDW	R2.SXTW, R10, R12               // 4cc1220b
	ADD	R19.UXTX, R14, R17              // d161338b
	ADDSW	R19.UXTW, R14, R17              // d141332b
	ADDS	R12.SXTX, R3, R1                // 61e02cab
	SUB	R19.UXTH<<4, R2, R21            // 553033cb
	SUBW	R1.UXTX<<1, R3, R2              // 6264214b

		register[s] = int16(i + x86.REG_AL)
	}
	// Pseudo-registers.
	register["SB"] = RSB
	register["FP"] = RFP
	register["PC"] = RPC
	if linkArch == &x86.Linkamd64 {
		// Alias g to R14
		register["g"] = x86.REGG
	}
	// Register prefix not used on this architecture.

	instructions := make(map[string]obj.As)
	for i, s := range obj.Anames {
		instructions[s] = obj.As(i)
	}