Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 7 of 7 for R14 (0.04 sec)

  1. lib/fips140/v1.1.0-rc1.zip

    P8_STXVB16X(V15, MASK_PTR, R0) CMP IN_LEN, $8 BLT next4 MOVD 0(MASK_PTR), R14 MOVD 0(BLK_INP), R15 XOR R14, R15, R14 MOVD R14, 0(BLK_OUT) ADD $8, R16 ADD $-8, IN_LEN next4: CMP IN_LEN, $4 BLT next2 MOVWZ (BLK_INP)(R16), R15 MOVWZ (MASK_PTR)(R16), R14 XOR R14, R15, R14 MOVW R14, (R16)(BLK_OUT) ADD $4, R16 ADD $-4, IN_LEN next2: CMP IN_LEN, $2 BLT next1 MOVHZ (BLK_INP)(R16), R15 MOVHZ (MASK_PTR)(R16), R14 XOR R14, R15, R14 MOVH R14, (R16)(BLK_OUT) ADD $2, R16 ADD $-2, IN_LEN next1: CMP IN_LEN, $1 BLT done...
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Dec 11 16:27:41 UTC 2025
    - 663K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	AMANDV		R14, (R13), R12 // acb96238
    	AMORW		R14, (R13), R12 // ac396338
    	AMORV		R14, (R13), R12 // acb96338
    	AMXORW		R14, (R13), R12 // ac396438
    	AMXORV		R14, (R13), R12 // acb96438
    	AMMAXW		R14, (R13), R12 // ac396538
    	AMMAXV		R14, (R13), R12 // acb96538
    	AMMINW		R14, (R13), R12 // ac396638
    	AMMINV		R14, (R13), R12 // acb96638
    	AMMAXWU		R14, (R13), R12 // ac396738
    	AMMAXVU		R14, (R13), R12 // acb96738
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Nov 27 00:46:52 UTC 2025
    - 44.5K bytes
    - Viewed (0)
  3. lib/fips140/v1.0.0-c2097c7c.zip

    P8_STXVB16X(V15, MASK_PTR, R0) CMP IN_LEN, $8 BLT next4 MOVD 0(MASK_PTR), R14 MOVD 0(BLK_INP), R15 XOR R14, R15, R14 MOVD R14, 0(BLK_OUT) ADD $8, R16 ADD $-8, IN_LEN next4: CMP IN_LEN, $4 BLT next2 MOVWZ (BLK_INP)(R16), R15 MOVWZ (MASK_PTR)(R16), R14 XOR R14, R15, R14 MOVW R14, (R16)(BLK_OUT) ADD $4, R16 ADD $-4, IN_LEN next2: CMP IN_LEN, $2 BLT next1 MOVHZ (BLK_INP)(R16), R15 MOVHZ (MASK_PTR)(R16), R14 XOR R14, R15, R14 MOVH R14, (R16)(BLK_OUT) ADD $2, R16 ADD $-2, IN_LEN next1: CMP IN_LEN, $1 BLT done...
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Sep 25 19:53:19 UTC 2025
    - 642.7K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/arm64.s

    	ADD	R2.SXTX<<1, RSP, RSP            // ffe7228b
    	ADD	ZR.SXTX<<1, R2, R3              // 43e43f8b
    	ADDW	R2.SXTW, R10, R12               // 4cc1220b
    	ADD	R19.UXTX, R14, R17              // d161338b
    	ADDSW	R19.UXTW, R14, R17              // d141332b
    	ADDS	R12.SXTX, R3, R1                // 61e02cab
    	SUB	R19.UXTH<<4, R2, R21            // 553033cb
    	SUBW	R1.UXTX<<1, R3, R2              // 6264214b
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Mon Nov 10 17:34:13 UTC 2025
    - 96.1K bytes
    - Viewed (0)
  5. src/test/java/jcifs/smb/NtlmUtilTest.java

            // Act
            byte[] r14 = NtlmUtil.getPreNTLMResponse(cifsContext, password14, challenge);
            byte[] r15 = NtlmUtil.getPreNTLMResponse(cifsContext, password15, challenge);
    
            // Assert: equal because only first 14 OEM bytes are used
            assertArrayEquals(r14, r15, "Only first 14 OEM bytes affect Pre-NTLM response");
            assertEquals(24, r14.length);
    
            // Verify collaborator interactions
    Registered: Sat Dec 20 13:44:44 UTC 2025
    - Last Modified: Sat Aug 30 05:58:03 UTC 2025
    - 12K bytes
    - Viewed (1)
  6. src/cmd/asm/internal/arch/arch.go

    		register[s] = int16(i + x86.REG_AL)
    	}
    	// Pseudo-registers.
    	register["SB"] = RSB
    	register["FP"] = RFP
    	register["PC"] = RPC
    	if linkArch == &x86.Linkamd64 {
    		// Alias g to R14
    		register["g"] = x86.REGG
    	}
    	// Register prefix not used on this architecture.
    
    	instructions := make(map[string]obj.As)
    	for i, s := range obj.Anames {
    		instructions[s] = obj.As(i)
    	}
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Nov 13 12:17:37 UTC 2025
    - 21.7K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/asm/testdata/arm64error.s

    TEXT errors(SB),$0
    	AND	$1, RSP                                          // ERROR "illegal source register"
    	ANDS	$1, R0, RSP                                      // ERROR "illegal combination"
    	ADDSW	R7->32, R14, R13                                 // ERROR "shift amount out of range 0 to 31"
    	ADD	R1.UXTB<<5, R2, R3                               // ERROR "shift amount out of range 0 to 4"
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Tue Oct 14 19:00:00 UTC 2025
    - 38.4K bytes
    - Viewed (0)
Back to top