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Results 1 - 10 of 29 for Bx (0.06 sec)
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src/crypto/md5/md5block_386.s
ROUND1(DX,AX,BX,CX, 6,0x4787c62a,12); ROUND1(CX,DX,AX,BX, 7,0xa8304613,17); ROUND1(BX,CX,DX,AX, 8,0xfd469501,22); ROUND1(AX,BX,CX,DX, 9,0x698098d8, 7); ROUND1(DX,AX,BX,CX,10,0x8b44f7af,12); ROUND1(CX,DX,AX,BX,11,0xffff5bb1,17); ROUND1(BX,CX,DX,AX,12,0x895cd7be,22); ROUND1(AX,BX,CX,DX,13,0x6b901122, 7); ROUND1(DX,AX,BX,CX,14,0xfd987193,12); ROUND1(CX,DX,AX,BX,15,0xa679438e,17);
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 4.5K bytes - Viewed (0) -
src/internal/runtime/atomic/atomic_amd64.s
TEXT ·StorepNoWB(SB), NOSPLIT, $0-16 MOVQ ptr+0(FP), BX MOVQ val+8(FP), AX XCHGQ AX, 0(BX) RET TEXT ·Store(SB), NOSPLIT, $0-12 MOVQ ptr+0(FP), BX MOVL val+8(FP), AX XCHGL AX, 0(BX) RET TEXT ·Store8(SB), NOSPLIT, $0-9 MOVQ ptr+0(FP), BX MOVB val+8(FP), AX XCHGB AX, 0(BX) RET TEXT ·Store64(SB), NOSPLIT, $0-16 MOVQ ptr+0(FP), BX MOVQ val+8(FP), AX XCHGQ AX, 0(BX) RET
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 5.2K bytes - Viewed (0) -
src/crypto/md5/md5block_amd64.s
MOVL c, R9; \ ADDL b, a ROUND1(AX,BX,CX,DX, 1,0xd76aa478, 7); ROUND1(DX,AX,BX,CX, 2,0xe8c7b756,12); ROUND1(CX,DX,AX,BX, 3,0x242070db,17); ROUND1(BX,CX,DX,AX, 4,0xc1bdceee,22); ROUND1(AX,BX,CX,DX, 5,0xf57c0faf, 7); ROUND1(DX,AX,BX,CX, 6,0x4787c62a,12); ROUND1(CX,DX,AX,BX, 7,0xa8304613,17); ROUND1(BX,CX,DX,AX, 8,0xfd469501,22); ROUND1(AX,BX,CX,DX, 9,0x698098d8, 7); ROUND1(DX,AX,BX,CX,10,0x8b44f7af,12);
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 4.8K bytes - Viewed (0) -
src/crypto/internal/edwards25519/field/fe_amd64.s
MULQ 16(BX) ADDQ AX, DI ADCQ DX, SI // r0 += 19×a4×b1 MOVQ 32(CX), AX IMUL3Q $0x13, AX, AX MULQ 8(BX) ADDQ AX, DI ADCQ DX, SI // r1 = a0×b1 MOVQ (CX), AX MULQ 8(BX) MOVQ AX, R9 MOVQ DX, R8 // r1 += a1×b0 MOVQ 8(CX), AX MULQ (BX) ADDQ AX, R9 ADCQ DX, R8 // r1 += 19×a2×b4 MOVQ 16(CX), AX IMUL3Q $0x13, AX, AX MULQ 32(BX) ADDQ AX, R9
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 5.7K bytes - Viewed (0) -
src/crypto/sha1/sha1block_386.s
ROUND1(BX, CX, DX, BP, AX, 4) ROUND1(AX, BX, CX, DX, BP, 5) ROUND1(BP, AX, BX, CX, DX, 6) ROUND1(DX, BP, AX, BX, CX, 7) ROUND1(CX, DX, BP, AX, BX, 8) ROUND1(BX, CX, DX, BP, AX, 9) ROUND1(AX, BX, CX, DX, BP, 10) ROUND1(BP, AX, BX, CX, DX, 11) ROUND1(DX, BP, AX, BX, CX, 12) ROUND1(CX, DX, BP, AX, BX, 13) ROUND1(BX, CX, DX, BP, AX, 14) ROUND1(AX, BX, CX, DX, BP, 15) ROUND1x(BP, AX, BX, CX, DX, 16)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 6K bytes - Viewed (0) -
src/internal/runtime/atomic/atomic_386.s
TEXT ·Or8(SB), NOSPLIT, $0-5 MOVL ptr+0(FP), AX MOVB val+4(FP), BX LOCK ORB BX, (AX) RET // void ·And8(byte volatile*, byte); TEXT ·And8(SB), NOSPLIT, $0-5 MOVL ptr+0(FP), AX MOVB val+4(FP), BX LOCK ANDB BX, (AX) RET TEXT ·Store8(SB), NOSPLIT, $0-5 MOVL ptr+0(FP), BX MOVB val+4(FP), AX XCHGB AX, 0(BX) RET // func Or(addr *uint32, v uint32)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 6.5K bytes - Viewed (0) -
src/crypto/sha1/sha1block_amd64.s
ROUND2(BX, CX, DX, BP, AX, 34) ROUND2(AX, BX, CX, DX, BP, 35) ROUND2(BP, AX, BX, CX, DX, 36) ROUND2(DX, BP, AX, BX, CX, 37) ROUND2(CX, DX, BP, AX, BX, 38) ROUND2(BX, CX, DX, BP, AX, 39) ROUND3(AX, BX, CX, DX, BP, 40) ROUND3(BP, AX, BX, CX, DX, 41) ROUND3(DX, BP, AX, BX, CX, 42) ROUND3(CX, DX, BP, AX, BX, 43) ROUND3(BX, CX, DX, BP, AX, 44) ROUND3(AX, BX, CX, DX, BP, 45)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 31.5K bytes - Viewed (0) -
src/runtime/asm_386.s
PUSHL AX PUSHL BX get_tls(BX) MOVL g(BX), BX LEAL arg+0(FP), AX MOVL AX, (g_sched+gobuf_sp)(BX) MOVL $runtime·systemstack_switch(SB), AX MOVL AX, (g_sched+gobuf_pc)(BX) MOVL $0, (g_sched+gobuf_ret)(BX) // Assert ctxt is zero. See func save. MOVL (g_sched+gobuf_ctxt)(BX), AX TESTL AX, AX JZ 2(PC) CALL runtime·abort(SB) POPL BX POPL AX RET
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 15 15:45:13 UTC 2024 - 43.1K bytes - Viewed (0) -
src/crypto/aes/asm_amd64.s
MOVQ nr+0(FP), CX MOVQ key+8(FP), AX MOVQ enc+16(FP), BX MOVQ dec+24(FP), DX MOVUPS (AX), X0 // enc MOVUPS X0, (BX) ADDQ $16, BX PXOR X4, X4 // _expand_key_* expect X4 to be zero CMPL CX, $12 JE Lexp_enc192 JB Lexp_enc128 Lexp_enc256: MOVUPS 16(AX), X2 MOVUPS X2, (BX) ADDQ $16, BX AESKEYGENASSIST $0x01, X2, X1 CALL _expand_key_256a<>(SB)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 5.4K bytes - Viewed (0) -
src/crypto/sha256/sha256block_386.s
RORL $19, CX; \ SHRL $10, DX; \ MOVL ((index-15)*4)(BP), BX; \ XORL CX, AX; \ MOVL BX, CX; \ XORL DX, AX; \ RORL $7, BX; \ MOVL CX, DX; \ SHRL $3, DX; \ RORL $18, CX; \ ADDL ((index-7)*4)(BP), AX; \ XORL CX, BX; \ XORL DX, BX; \ ADDL ((index-16)*4)(BP), BX; \ ADDL BX, AX; \ MOVL AX, ((index)*4)(BP) // Calculate T1 in AX - uses AX, BX, CX and DX registers. // Wt is passed in AX.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 8.2K bytes - Viewed (0)