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Results 1 - 6 of 6 for ximm (0.03 sec)
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src/cmd/asm/internal/asm/testdata/mips.s
// } SLL R1, R2 // LSHW imm ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // } SLL $4, R1, R2 // LSHW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } SLL $4, R1 // // move immediate: macro for lui+or, addi, addis, and other combinations // // LMOVW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // }
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 6.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
ROTRV R16, R9 // 02094856 // LSHW imm ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // } SLL $19, R22, R21 // 0016acc0 SLLV $19, R22, R21 // 0016acf8 SRL $31, R6, R17 // 00068fc2 SRLV $31, R6, R17 // 00068ffa SRA $8, R8, R19 // 00089a03 SRAV $19, R8, R7 // 00083cfb ROTR $12, R8, R3 // 00281b02 ROTRV $8, R22, R22 // 0036b23a // LSHW imm ',' rreg // {
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
// // SWAP // // LTYPE9 cond reg ',' ireg ',' reg // { // outcode($1, $2, &$5, int32($3.Reg), &$7); // } STREX R1, (R2), R3 // STREX (R2), R1, R3 // // word // // LTYPEH comma ximm // { // outcode($1, Always, &nullgen, 0, &$3); // } WORD $1234 // // floating-point coprocessor // // LTYPEI cond freg ',' freg // { // outcode($1, $2, &$3, 0, &$5); // }
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0) -
src/cmd/asm/internal/lex/lex_test.go
"\n.\n.MOVBLZX.(.8.*.4.).(.R12.).,.AX.\n.ADDB.AX.,.DX.\n", }, { "nested multiline macro", lines( "#define KEYROUND(xmm, load, off, r1, r2, index) \\", "\tMOVBLZX (BP)(DX*4), R8 \\", "\tload((off+1), r2) \\", "\tMOVB R8, (off*4)(R12) \\", "\tPINSRW $index, (BP)(R8*4), xmm", "#define LOAD(off, reg) \\", "\tMOVBLZX (off*4)(R12), reg \\", "\tADDB reg, DX", "KEYROUND(X0, LOAD, 8, AX, BX, 0)",
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Aug 29 07:48:38 UTC 2023 - 5.8K bytes - Viewed (0) -
doc/asm.html
</li> <li> <code>R0.UXTB</code> <br> <code>R0.UXTB<<imm</code>: <code>UXTB</code>: extract an 8-bit value from the low-order bits of <code>R0</code> and zero-extend it to the size of <code>R0</code>. <code>R0.UXTB<<imm</code>: left shift the result of <code>R0.UXTB</code> by <code>imm</code> bits. The <code>imm</code> value can be 0, 1, 2, 3, or 4.
Registered: Tue Nov 05 11:13:11 UTC 2024 - Last Modified: Tue Nov 28 19:15:27 UTC 2023 - 36.3K bytes - Viewed (0) -
docs/de/docs/features.md
Registered: Sun Nov 03 07:19:11 UTC 2024 - Last Modified: Thu Aug 15 23:30:12 UTC 2024 - 10.7K bytes - Viewed (0)