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Results 1 - 3 of 3 for VLSEG2E8V (0.05 sec)

  1. src/cmd/asm/internal/asm/testdata/riscv64validation.s

    	VSOXEI8V	V3, V2, (V1)			// ERROR "expected integer register in rs1 position"
    	VSOXEI8V	V3, X11, V0, (X10)		// ERROR "expected vector register in vs2 position"
    	VLSEG2E8V	(X10), X10			// ERROR "expected vector register in vd position"
    	VLSEG2E8V	(V1), V3			// ERROR "expected integer register in rs1 position"
    	VLSEG2E8FFV	(X10), X10			// ERROR "expected vector register in vd position"
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Nov 13 12:17:37 UTC 2025
    - 42.1K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/riscv64error.s

    	VSUXEI8V	V3, V2, V1, (X10)		// ERROR "invalid vector mask register"
    	VLOXEI8V	(X10), V2, V1, V3		// ERROR "invalid vector mask register"
    	VSOXEI8V	V3, V2, V1, (X10)		// ERROR "invalid vector mask register"
    	VLSEG2E8V	(X10), V1, V3			// ERROR "invalid vector mask register"
    	VLSEG2E8FFV	(X10), V1, V3			// ERROR "invalid vector mask register"
    	VSSEG2E8V	V3, V1, (X10)			// ERROR "invalid vector mask register"
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Wed Sep 24 13:21:53 UTC 2025
    - 26.8K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/riscv64.s

    	// 31.7.8: Vector Load/Store Segment Instructions
    
    	// 31.7.8.1: Vector Unit-Stride Segment Loads and Stores
    	VLSEG2E8V	(X10), V8			// 07040522
    	VLSEG2E16V	(X10), V8			// 07540522
    	VLSEG2E32V	(X10), V8			// 07640522
    	VLSEG2E64V	(X10), V8			// 07740522
    	VLSEG2E8V	(X10), V0, V8			// 07040520
    	VLSEG2E16V	(X10), V0, V8			// 07540520
    	VLSEG2E32V	(X10), V0, V8			// 07640520
    	VLSEG2E64V	(X10), V0, V8			// 07740520
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Nov 13 12:17:37 UTC 2025
    - 73.7K bytes
    - Viewed (0)
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