- Sort Score
- Result 10 results
- Languages All
Results 1 - 4 of 4 for MSR (0.18 sec)
-
src/cmd/asm/internal/asm/testdata/arm64error.s
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Mar 26 10:48:50 UTC 2025 - 37.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
MSR R29, PMEVCNTR16_EL0 // 1dea1bd5 MSR R11, PMEVCNTR17_EL0 // 2bea1bd5 MSR R16, PMEVCNTR18_EL0 // 50ea1bd5 MSR R2, PMEVCNTR19_EL0 // 62ea1bd5 MSR R19, PMEVCNTR20_EL0 // 93ea1bd5 MSR R17, PMEVCNTR21_EL0 // b1ea1bd5 MSR R7, PMEVCNTR22_EL0 // c7ea1bd5 MSR R23, PMEVCNTR23_EL0 // f7ea1bd5
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Mar 26 10:48:50 UTC 2025 - 95.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
MOVD $0, R5 // e5031faa MSR $1, SPSel // bf4100d5 MSR $9, DAIFSet // df4903d5 MSR $6, DAIFClr // ff4603d5 MRS ELR_EL1, R8 // 284038d5 MSR R16, ELR_EL1 // 304018d5 MRS DCZID_EL0, R3 // e3003bd5
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arch.go
} register["CR"] = ppc64.REG_CR register["XER"] = ppc64.REG_XER register["LR"] = ppc64.REG_LR register["CTR"] = ppc64.REG_CTR register["FPSCR"] = ppc64.REG_FPSCR register["MSR"] = ppc64.REG_MSR // Pseudo-registers. register["SB"] = RSB register["FP"] = RFP register["PC"] = RPC // Avoid unintentionally clobbering g using R30. delete(register, "R30") register["g"] = ppc64.REG_R30
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Thu Nov 07 02:20:14 UTC 2024 - 21.7K bytes - Viewed (0)