VFMLA	V1.B16, V12.B16, V3.B16                          // ERROR "invalid arrangement"
	VFMLA	V1.H4, V12.H4, V3.H4                             // ERROR "invalid arrangement"
	VFMLA	V1.H8, V12.H8, V3.H8                             // ERROR "invalid arrangement"
	VFMLA	V1.H4, V12.H4, V3.H4                             // ERROR "invalid arrangement"

	UCVTFD R20, F11                            // 8b02639e
	VADD V16, V19, V14                                          // 6e86f05e
	VADD V5.H8, V18.H8, V9.H8                                   // 4986654e
	VADDP V7.H8, V25.H8, V17.H8                                 // 31bf674e
	VADDV V3.H8, V0                                             // 60b8714e
	AESD V22.B16, V19.B16                                       // d35a284e

	VUMAX	V3.H4, V2.H4, V1.H4             // 4164632e
	VUMAX	V3.H8, V2.H8, V1.H8             // 4164636e
	VUMAX	V3.S2, V2.S2, V1.S2             // 4164a32e
	VUMAX	V3.S4, V2.S4, V1.S4             // 4164a36e
	VUMIN	V3.B8, V2.B8, V1.B8             // 416c232e
	VUMIN	V3.B16, V2.B16, V1.B16          // 416c236e
	VUMIN	V3.H4, V2.H4, V1.H4             // 416c632e
	VUMIN	V3.H8, V2.H8, V1.H8             // 416c636e

	"V":  loong64.ARNG_V,
	"BU": loong64.ARNG_BU,
	"HU": loong64.ARNG_HU,
	"WU": loong64.ARNG_WU,
	"VU": loong64.ARNG_VU,
}

var loong64LsxArngExtMap = map[string]int16{
	"B16": loong64.ARNG_16B,
	"H8":  loong64.ARNG_8H,
	"W4":  loong64.ARNG_4W,
	"V2":  loong64.ARNG_2V,
}

var loong64LasxArngExtMap = map[string]int16{
	"B32": loong64.ARNG_32B,
	"H16": loong64.ARNG_16H,
	"W8":  loong64.ARNG_8W,

		case "H4":
			if isIndex {
				return errors.New("invalid register extension")
			}
			a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4H & 15) << 5)
		case "H8":
			if isIndex {
				return errors.New("invalid register extension")
			}
			a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8H & 15) << 5)
		case "S2":
			if isIndex {

	VMOVQ		V2.H[2], V8.H8  // 48c8f772
	VMOVQ		V3.W[1], V7.W4  // 67e4f772
	VMOVQ		V4.V[0], V6.V2  // 86f0f772

	// Load data from memory and broadcast to each element of a vector register: VMOVQ    offset(Rj), <Vd>.<T>
	VMOVQ		(R4), V0.B16	// 80008030
	VMOVQ		1(R4), V0.B16	// 80048030
	VMOVQ		-3(R4), V0.B16	// 80f4bf30
	VMOVQ		(R4), V1.H8	// 81004030
	VMOVQ		2(R4), V1.H8	// 81044030
	VMOVQ		-6(R4), V1.H8	// 81f45f30

V18(W0+K0...W3+K3) SHA256SU0 V5.S4, V4.S4 // V4: (su0(W1)+W0,...,su0(W4)+W3) HASHUPDATE // H4 VADD V17.S4, V5.S4, V9.S4 // V18(W4+K4...W7+K7) SHA256SU0 V6.S4, V5.S4 // V5: (su0(W5)+W4,...,su0(W8)+W7) SHA256SU1 V7.S4, V6.S4, V4.S4 // V4: W16-W19 HASHUPDATE // H8 VADD V18.S4, V6.S4, V9.S4 // V18(W8+K8...W11+K11) SHA256SU0 V7.S4, V6.S4 // V6: (su0(W9)+W8,...,su0(W12)+W11) SHA256SU1 V4.S4, V7.S4, V5.S4 // V5: W20-W23 HASHUPDATE // H12 VADD V19.S4, V7.S4, V9.S4 // V18(W12+K12...W15+K15) SHA256SU0 V4.S4, V7.S4 //...