VMOVB	$511, W0   // 7b0ff807
	VMOVH	$24, W23   // 7b20c5c7
	VMOVW	$-24, W15  // 7b5f43c7
	VMOVD	$-511, W31 // 7b700fc7

	VMOVB	(R0), W8       // 78000220
	VMOVB	511(R3), W0    // 79ff1820
	VMOVB	-512(R12), W21 // 7a006560
	VMOVH	(R24), W12     // 7800c321
	VMOVH	110(R19), W8   // 78379a21
	VMOVH	-70(R12), W3   // 7bdd60e1
	VMOVW	(R3), W31      // 78001fe2
	VMOVW	64(R20), W16   // 7810a422

	"B16": loong64.ARNG_16B,
	"H8":  loong64.ARNG_8H,
	"W4":  loong64.ARNG_4W,
	"V2":  loong64.ARNG_2V,
}

var loong64LasxArngExtMap = map[string]int16{
	"B32": loong64.ARNG_32B,
	"H16": loong64.ARNG_16H,
	"W8":  loong64.ARNG_8W,
	"V4":  loong64.ARNG_4V,
	"Q2":  loong64.ARNG_2Q,
}

// Loong64RegisterExtension constructs an Loong64 register with extension or arrangement.

	XVMOVQ		-5(R4), X0.B32	// 80ecbf32
	XVMOVQ		(R4), X1.H16	// 81004032
	XVMOVQ		2(R4), X1.H16	// 81044032
	XVMOVQ		-10(R4), X1.H16	// 81ec5f32
	XVMOVQ		(R4), X2.W8	// 82002032
	XVMOVQ		8(R4), X2.W8	// 82082032
	XVMOVQ		-20(R4), X2.W8	// 82ec2f32
	XVMOVQ		(R4), X3.V4	// 83001032
	XVMOVQ		24(R4), X3.V4	// 830c1032
	XVMOVQ		-24(R4), X3.V4	// 83f41732

	// VSEQ{B,H,W,V}, XVSEQ{B,H,W,V} instruction

SHA256SU0 V5.S4, V4.S4 // V4: (su0(W1)+W0,...,su0(W4)+W3) HASHUPDATE // H4 VADD V17.S4, V5.S4, V9.S4 // V18(W4+K4...W7+K7) SHA256SU0 V6.S4, V5.S4 // V5: (su0(W5)+W4,...,su0(W8)+W7) SHA256SU1 V7.S4, V6.S4, V4.S4 // V4: W16-W19 HASHUPDATE // H8 VADD V18.S4, V6.S4, V9.S4 // V18(W8+K8...W11+K11) SHA256SU0 V7.S4, V6.S4 // V6: (su0(W9)+W8,...,su0(W12)+W11) SHA256SU1 V4.S4, V7.S4, V5.S4 // V5: W20-W23 HASHUPDATE // H12 VADD V19.S4, V7.S4, V9.S4 // V18(W12+K12...W15+K15) SHA256SU0 V4.S4, V7.S4 // V7: (su0(W...