ARM.HasIDIVA = isSet(HWCap, hwcap_IDIVA)
	// lpae is required to make the 64-bit instructions LDRD and STRD (and variants) atomic.
	// See ARMv7 manual section B1.6.
	// We also need at least a v7 chip, for the DMB instruction.
	ARM.HasV7Atomics = isSet(HWCap, hwcap_LPAE) && isV7(Platform)
}

func isSet(hwc uint, value uint) bool {
	return hwc&value != 0
}

func isV7(s string) bool {
	if s == "aarch64" {

// license that can be found in the LICENSE file.

//go:build amd64 || arm64

package ssa

// This file tests the functions addFlags64 and subFlags64 by comparing their
// results to what the chip calculates.

import (
	"runtime"
	"testing"
)

func TestAddFlagsNative(t *testing.T) {
	var numbers = []int64{
		1, 0, -1,
		2, -2,
		1<<63 - 1, -1 << 63,
	}
	coverage := map[flagConstant]bool{}

	HasPCLMULQDQ        bool // PCLMULQDQ instruction - most often used for AES-GCM
	HasPOPCNT           bool // Hamming weight instruction POPCNT.
	HasRDRAND           bool // RDRAND instruction (on-chip random number generator)
	HasRDSEED           bool // RDSEED instruction (on-chip random number generator)
	HasSSE2             bool // Streaming SIMD extension 2 (always available on amd64)
	HasSSE3             bool // Streaming SIMD extension 3

    This pass sets the device ordinal attribute of the ops using the replica id
    attribute. This is run immediately after the replica_to_island pass which
    sets the replica id attribute of these ops. Note for single chip usecase,
    the pass will check if there is one op and sets the device ordinal attribute
    to be zero.
  }];
}

def ConvertReadonlyReferenceVariablesToResourceVariablesPass :

	EM_Z80           Machine = 220 /* Zilog Z80 */
	EM_VISIUM        Machine = 221 /* Controls and Data Services VISIUMcore processor */
	EM_FT32          Machine = 222 /* FTDI Chip FT32 high performance 32-bit RISC architecture */
	EM_MOXIE         Machine = 223 /* Moxie processor family */
	EM_AMDGPU        Machine = 224 /* AMD GPU architecture */
	EM_RISCV         Machine = 243 /* RISC-V */

This pass sets the device ordinal attribute of the ops using the replica id
attribute. This is run immediately after the replica_to_island pass which
sets the replica id attribute of these ops. Note for single chip usecase,
the pass will check if there is one op and sets the device ordinal attribute
to be zero.
### `-tf-replicate-invariant-op-hoisting`

_Hoists replicate invariant operations out of replicate_

	//   to continue receiving logs, so it cannot be start or
	//   stop;
	if (hip.forceStart && hip.forceStop) ||
		(hip.clientToken != "" && (hip.forceStart || hip.forceStop)) {
		err = ErrInvalidRequest
		return
	}

	// ignore body if clientToken is provided
	if hip.clientToken == "" {
		jerr := json.NewDecoder(r).Decode(&hip.hs)
		if jerr != nil {
			adminLogIf(GlobalContext, jerr, logger.ErrorKind)

    pluginsRuntimeOnly(project(":scala"))
    pluginsRuntimeOnly(project(":war"))

    pluginsRuntimeOnly(project(":java-platform")) {
        because("Aspirationally, we likely need a platform-base plugin that would ship in the same distribution as dependency-management, and isn't java specific - unfortunately this plugin applies the JvmEcosystemPlugin.")
    }

    Arg<TF_VariantTensor, [{A Tensor with type=DT_VARIANT containing the deduplication
data. The tensor is an XLA nested tuple containing N elements (where N is
the ratio of the number of embedding to tensor cores per TPU chip). Each
element of the nested tuple is a tuple of rank 1 tensors. Each tensor either
contains indices (DT_UINT32) for embedding lookup on the TensorCore or

This helps to identify any possible issues with the build that may affect cacheability.

If you are subject to audit requirements regarding the artifacts you ship to your customers you may need to disable the build cache for certain builds.
Develocity may help you with fulfilling these requirements while still using the build cache for all your builds.