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  1. src/cmd/asm/internal/asm/testdata/riscv64.s

    	// 28.4.2: Bitwise Rotation (Zbb)
    	ROL	X8, X9, X10				// 33958460 or b30f8040b3dff4013395840033e5af00
    	ROL	X8, X9					// b3948460 or b30f8040b3dff401b3948400b3e49f00
    	ROLW	X9, X10, X11				// bb159560 or b30f9040bb5ff501bb159500b3e5bf00
    	ROLW	X9, X10					// 3b159560 or b30f9040bb5ff5013b15950033e5af00
    	ROR	X10, X11, X12				// 33d6a560 or b30fa040b39ff50133d6a50033e6cf00
    	ROR	X10, X11				// b3d5a560 or b30fa040b39ff501b3d5a500b3e5bf00
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Fri Oct 25 12:05:29 UTC 2024
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