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Results 1 - 4 of 4 for SRLI (0.2 sec)

  1. src/cmd/asm/internal/asm/testdata/riscv64error.s

    	SLLI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
    	SRLI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
    	SRAI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
    	RORI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
    	SLLI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
    	SRLI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 2.8K bytes
    - Viewed (0)
  2. test/codegen/shift.go

    // ------------------ //
    
    func lshConst64x64(v int64) int64 {
    	// ppc64x:"SLD"
    	// riscv64:"SLLI",-"AND",-"SLTIU"
    	return v << uint64(33)
    }
    
    func rshConst64Ux64(v uint64) uint64 {
    	// ppc64x:"SRD"
    	// riscv64:"SRLI\t",-"AND",-"SLTIU"
    	return v >> uint64(33)
    }
    
    func rshConst64Ux64Overflow32(v uint32) uint64 {
    	// riscv64:"MOV\t\\$0,",-"SRL"
    	return uint64(v) >> 32
    }
    
    func rshConst64Ux64Overflow16(v uint16) uint64 {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 21 18:53:43 UTC 2024
    - 12.7K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/riscv/obj.go

    				ins.as, ins.rs1, ins.rs2, ins.imm = AZEXTH, uint32(p.From.Reg), obj.REG_NONE, 0
    				if p.As == AMOVWU {
    					ins.as, ins.rs2 = AADDUW, REG_ZERO
    				}
    			} else {
    				// Use SLLI/SRLI sequence to extend.
    				ins.as, ins.rs1, ins.rs2 = ASLLI, uint32(p.From.Reg), obj.REG_NONE
    				if p.As == AMOVHU {
    					ins.imm = 48
    				} else if p.As == AMOVWU {
    					ins.imm = 32
    				}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 77K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/opGen.go

    			},
    			outputs: []outputInfo{
    				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
    			},
    		},
    	},
    	{
    		name:    "SRLI",
    		auxType: auxInt64,
    		argLen:  1,
    		asm:     riscv.ASRLI,
    		reg: regInfo{
    			inputs: []inputInfo{
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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