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  1. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	MOVBU.P 42(R2), R12                        // 4ca44238
    	MOVBU.W -27(R2), R14                       // 4e5c5e38
    	MOVBU 2916(R24), R3                        // 03936d39
    	MOVBU (R19)(R14<<0), R23                   // 776a6e38
    	MOVBU (R2)(R8.SXTX), R19                   // 53e86838
    	MOVBU (R27)(R23), R14                      // 6e6b7738
    	MOVHU.P 107(R14), R13                      // cdb54678
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Tue Feb 24 21:29:25 GMT 2026
    - 44K bytes
    - Click Count (0)
  2. src/cmd/asm/internal/asm/testdata/arm64.s

    	ADD	R2.SXTX<<1, RSP, RSP            // ffe7228b
    	ADD	ZR.SXTX<<1, R2, R3              // 43e43f8b
    	ADDW	R2.SXTW, R10, R12               // 4cc1220b
    	ADD	R19.UXTX, R14, R17              // d161338b
    	ADDSW	R19.UXTW, R14, R17              // d141332b
    	ADDS	R12.SXTX, R3, R1                // 61e02cab
    	SUB	R19.UXTH<<4, R2, R21            // 553033cb
    	SUBW	R1.UXTX<<1, R3, R2              // 6264214b
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Fri Feb 27 20:41:17 GMT 2026
    - 96.2K bytes
    - Click Count (0)
  3. src/cmd/asm/internal/arch/arch.go

    		register[s] = int16(i + x86.REG_AL)
    	}
    	// Pseudo-registers.
    	register["SB"] = RSB
    	register["FP"] = RFP
    	register["PC"] = RPC
    	if linkArch == &x86.Linkamd64 {
    		// Alias g to R14
    		register["g"] = x86.REGG
    	}
    	// Register prefix not used on this architecture.
    
    	instructions := make(map[string]obj.As)
    	for i, s := range obj.Anames {
    		instructions[s] = obj.As(i)
    	}
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Fri Mar 20 17:02:17 GMT 2026
    - 22K bytes
    - Click Count (0)
  4. src/cmd/asm/internal/asm/testdata/arm64error.s

    TEXT errors(SB),$0
    	AND	$1, RSP                                          // ERROR "illegal source register"
    	ANDS	$1, R0, RSP                                      // ERROR "illegal combination"
    	ADDSW	R7->32, R14, R13                                 // ERROR "shift amount out of range 0 to 31"
    	ADD	R1.UXTB<<5, R2, R3                               // ERROR "shift amount out of range 0 to 4"
    Created: Tue Apr 07 11:13:11 GMT 2026
    - Last Modified: Tue Feb 24 21:29:25 GMT 2026
    - 38.5K bytes
    - Click Count (0)
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