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Results 1 - 4 of 4 for fpscr (0.01 sec)
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src/cmd/asm/internal/arch/arch.go
register[obj.Rconv(i)] = int16(i) } register["CR"] = ppc64.REG_CR register["XER"] = ppc64.REG_XER register["LR"] = ppc64.REG_LR register["CTR"] = ppc64.REG_CTR register["FPSCR"] = ppc64.REG_FPSCR register["MSR"] = ppc64.REG_MSR // Pseudo-registers. register["SB"] = RSB register["FP"] = RFP register["PC"] = RPC // Avoid unintentionally clobbering g using R30.
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Thu Nov 07 02:20:14 UTC 2024 - 21.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/armerror.s
MOVM.DB [R0-R4], 4(R1) // ERROR "offset must be zero" MOVW CPSR, FPSR // ERROR "illegal combination" MOVW FPSR, CPSR // ERROR "illegal combination" MOVW CPSR, errors(SB) // ERROR "illegal combination" MOVW errors(SB), CPSR // ERROR "illegal combination" MOVW FPSR, errors(SB) // ERROR "illegal combination" MOVW errors(SB), FPSR // ERROR "illegal combination" MOVW F0, errors(SB) // ERROR "illegal combination"
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Oct 23 15:18:14 UTC 2024 - 14.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
MRS FAR_EL1, R9 // 096038d5 MSR R25, FAR_EL1 // 196018d5 MRS FPCR, R1 // 01443bd5 MSR R27, FPCR // 1b441bd5 MRS FPSR, R5 // 25443bd5 MSR R15, FPSR // 2f441bd5 MRS ID_AA64AFR0_EL1, R19 // 930538d5 MRS ID_AA64AFR1_EL1, R24 // b80538d5
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Mar 26 10:48:50 UTC 2025 - 95.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0)