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Results 1 - 3 of 3 for VLUXSEG2EI8V (0.09 sec)
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src/cmd/asm/internal/asm/testdata/riscv64validation.s
VSSSEG2E8V V3, V1, V0, (X10) // ERROR "expected integer register in rs2 position" VLUXSEG2EI8V (X10), V2, X11 // ERROR "expected vector register in vd position" VLUXSEG2EI8V (X10), V2, X11 // ERROR "expected vector register in vd position" VLUXSEG2EI8V (V1), V2, V3 // ERROR "expected integer register in rs1 position" VLUXSEG2EI8V (X10), X11, V0, V3 // ERROR "expected vector register in vs2 position"
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 13 12:17:37 UTC 2025 - 42.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64error.s
VSSEG2E8V V3, V1, (X10) // ERROR "invalid vector mask register" VLSSEG2E8V (X10), X10, V1, V3 // ERROR "invalid vector mask register" VSSSEG2E8V V3, X11, V1, (X10) // ERROR "invalid vector mask register" VLUXSEG2EI8V (X10), V2, V1, V3 // ERROR "invalid vector mask register" VSUXSEG2EI8V V3, V2, V1, (X10) // ERROR "invalid vector mask register" VLOXSEG2EI8V (X10), V2, V1, V3 // ERROR "invalid vector mask register"
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Wed Sep 24 13:21:53 UTC 2025 - 26.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
VSSSEG8E64V V24, X11, V0, (X10) // 277cb5e8 // 31.7.8.3: Vector Indexed Segment Loads and Stores VLUXSEG2EI8V (X10), V4, V8 // 07044526 VLUXSEG2EI16V (X10), V4, V8 // 07544526 VLUXSEG2EI32V (X10), V4, V8 // 07644526 VLUXSEG2EI64V (X10), V4, V8 // 07744526 VLUXSEG2EI8V (X10), V4, V0, V8 // 07044524 VLUXSEG2EI16V (X10), V4, V0, V8 // 07544524 VLUXSEG2EI32V (X10), V4, V0, V8 // 07644524
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 13 12:17:37 UTC 2025 - 73.7K bytes - Viewed (0)