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Results 1 - 3 of 3 for VLSSEG2E8V (0.04 sec)
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src/cmd/asm/internal/asm/testdata/riscv64validation.s
VSSEG2E8V V3, (V1) // ERROR "expected integer register in rd position" VLSSEG2E8V (X10), V3 // ERROR "expected integer register in rs2 position" VLSSEG2E8V (X10), X10, X11 // ERROR "expected vector register in vd position" VLSSEG2E8V (V1), X10, V3 // ERROR "expected integer register in rs1 position" VLSSEG2E8V (X10), V1, V0, V3 // ERROR "expected integer register in rs2 position"
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 13 12:17:37 UTC 2025 - 42.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64error.s
VLSEG2E8V (X10), V1, V3 // ERROR "invalid vector mask register" VLSEG2E8FFV (X10), V1, V3 // ERROR "invalid vector mask register" VSSEG2E8V V3, V1, (X10) // ERROR "invalid vector mask register" VLSSEG2E8V (X10), X10, V1, V3 // ERROR "invalid vector mask register" VSSSEG2E8V V3, X11, V1, (X10) // ERROR "invalid vector mask register" VLUXSEG2EI8V (X10), V2, V1, V3 // ERROR "invalid vector mask register"
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Wed Sep 24 13:21:53 UTC 2025 - 26.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
VLSEG8E64FFV (X10), V0, V8 // 077405e1 // 31.7.8.2: Vector Strided Segment Loads and Stores VLSSEG2E8V (X10), X11, V8 // 0704b52a VLSSEG2E16V (X10), X11, V8 // 0754b52a VLSSEG2E32V (X10), X11, V8 // 0764b52a VLSSEG2E64V (X10), X11, V8 // 0774b52a VLSSEG2E8V (X10), X11, V0, V8 // 0704b528 VLSSEG2E16V (X10), X11, V0, V8 // 0754b528 VLSSEG2E32V (X10), X11, V0, V8 // 0764b528
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 13 12:17:37 UTC 2025 - 73.7K bytes - Viewed (0)