PRELDX	0(R7), $0x80001021, $0		// PRELDX (R7), $2147487777, $0		// 1e020014de0380031e000016de130003e0782c38
	PRELDX	-1(R7), $0x1021, $2		// PRELDX -1(R7), $4129, $2		// fe030014deffbf031e000016de030003e2782c38
	PRELDX	8(R7), $0x80100800, $31		// PRELDX 8(R7), $2148534272, $31	// 1ee00714de238003fe1f0016de130003ff782c38

	XORW	(R1), R2              // 57201000
	XORW	-1(R1), R2            // e3201fffff57

	// shift and rotate instructions
	SRD	$4, R4, R7              // eb740004000c
	SRD	R1, R4, R7              // eb741000000c
	SRW	$4, R4, R7              // eb74000400de
	SRW	R1, R4, R7              // eb74100000de
	SLW	$4, R3, R6              // eb63000400df
	SLW	R2, R3, R6              // eb63200000df

	TST	$4278190080, R9      // ff0419e3
	TST	R9<<30, R7           // 090f17e1
	TST	R9>>30, R7           // 290f17e1
	TST	R9->30, R7           // 490f17e1
	TST	R9@>30, R7           // 690f17e1
	TST	R9<<R8, R7           // 190817e1
	TST	R9>>R8, R7           // 390817e1
	TST	R9->R8, R7           // 590817e1
	TST	R9@>R8, R7           // 790817e1

// CMP
	CMP	$255, R7             // ff0057e3

	MOVD	$0x2001(R7), R1               // MOVD	$8193(R7), R1               // e108409121040091
	MOVD	$0xffffff(R7), R1             // MOVD	$16777215(R7), R1           // e1fc7f9121fc3f91
	MOVD	$-0x1(R7), R1                 // MOVD	$-1(R7), R1                 // e10400d1
	MOVD	$-0x30(R7), R1                // MOVD	$-48(R7), R1                // e1c000d1

	ADDS	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	ADDSW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUB	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUBW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"

	OR $65535, R5, R6               // 60a6ffff
	OR $65536, R6                   // 64c60001
	OR $65536, R6, R7               // 64c70001
	OR $-32767, R5                  // 3be080017fe52b78
	OR $-32767, R5, R6              // 3be080017fe62b78
	OR $-32768, R6                  // 3be080007fe63378
	OR $-32768, R6, R7              // 3be080007fe73378
	OR $1234567, R5                 // 64a5001260a5d687

	MOVW.S	$0xaaaaaaaa, R7    // ERROR "invalid .S suffix"
	MOVW.P	$0xffffff44, R1    // ERROR "invalid .P suffix"
	MOVW.S	$0xffffff77, R1    // ERROR "invalid .S suffix"
	MVN.S	$0xffffffaa, R8    // ERROR "invalid .S suffix"
	MVN.S	$0xaaaaaaaa, R8    // ERROR "invalid .S suffix"
	ADD.U	$0xaaaaaaaa, R4    // ERROR "invalid .U suffix"
	ORR.P	$0x555555, R7, R3  // ERROR "invalid .P suffix"

	VMOVQ		V4.H[2], R6     // 86c8ef72
	VMOVQ		V5.W[2], R7     // a7e8ef72
	VMOVQ		V6.V[1], R8     // c8f4ef72
	VMOVQ		V7.BU[0], R4    // e480f372
	VMOVQ		V7.BU[1], R4    // e484f372
	VMOVQ		V9.BU[3], R5    // 258df372
	VMOVQ		V10.HU[2], R6   // 46c9f372
	VMOVQ		V11.WU[2], R7   // 67e9f372
	VMOVQ		V31.VU[1], R8   // e8f7f372
	XVMOVQ		X1.W[2], R7     // 27c8ef76
	XVMOVQ		X6.V[2], R8     // c8e8ef76

·xorBytes(SB), NOSPLIT, $0 MOVV dst+0(FP), R4 MOVV a+8(FP), R5 MOVV b+16(FP), R6 MOVV n+24(FP), R7 MOVV $64, R9 BGEU R7, R9, loop64 // n >= 64 tail: SRLV $1, R9 BGEU R7, R9, xor_32 // n >= 32 && n < 64 SRLV $1, R9 BGEU R7, R9, xor_16 // n >= 16 && n < 32 SRLV $1, R9 BGEU R7, R9, xor_8 // n >= 8 && n < 16 SRLV $1, R9 BGEU R7, R9, xor_4 // n >= 4 && n < 8 SRLV $1, R9 BGEU R7, R9, xor_2 // n >= 2 && n < 4 SRLV $1, R9 BGEU R7, R9, xor_1 // n = 1 loop64: MOVV (R5), R10 MOVV 8(R5), R11 MOVV 16(R5), R12 MOVV 24(R5),...

The range of registers is specified by a start register and an end register.
For example, <code>LMG</code> <code>(R9),</code> <code>R5,</code> <code>R7</code> would load
<code>R5</code>, <code>R6</code> and <code>R7</code> with the 64-bit values at
<code>0(R9)</code>, <code>8(R9)</code> and <code>16(R9)</code> respectively.
</p>

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