MOVBU.P 42(R2), R12                        // 4ca44238
	MOVBU.W -27(R2), R14                       // 4e5c5e38
	MOVBU 2916(R24), R3                        // 03936d39
	MOVBU (R19)(R14<<0), R23                   // 776a6e38
	MOVBU (R2)(R8.SXTX), R19                   // 53e86838
	MOVBU (R27)(R23), R14                      // 6e6b7738
	MOVHU.P 107(R14), R13                      // cdb54678

//	}
	ADD	R5, R9, R10	// 01255020
	ADDU	R13, R14, R19	// 01cd9821
	ADDV	R5, R9, R10	// 0125502c
	ADDVU	R13, R14, R19	// 01cd982d

//	LADDW imm ',' sreg ',' rreg
//	{
//		outcode(int($1), &$2, int($4), &$6);
//	}
	ADD	$15176, R14, R9	// 21c93b48
	ADD	$-9, R5, R8	// 20a8fff7
	ADDU	$10, R9, R9	// 2529000a
	ADDV	$15176, R14, R9	// 61c93b48
	ADDV	$-9, R5, R8	// 60a8fff7

	{"BX", "BX"},
	{"CX", "CX"},
	{"DI", "DI"},
	{"DX", "DX"},
	{"R10", "R10"},
	{"R10", "R10"},
	{"R11", "R11"},
	{"R12", "R12"},
	{"R13", "R13"},
	{"R14", "R14"},
	{"R15", "R15"},
	{"R8", "R8"},
	{"R9", "R9"},
	{"g", "R14"},
	{"SI", "SI"},
	{"SP", "SP"},
	{"X0", "X0"},
	{"X1", "X1"},
	{"X10", "X10"},
	{"X11", "X11"},
	{"X12", "X12"},
	{"X13", "X13"},
	{"X14", "X14"},

	ADD	R2.SXTX<<1, RSP, RSP            // ffe7228b
	ADD	ZR.SXTX<<1, R2, R3              // 43e43f8b
	ADDW	R2.SXTW, R10, R12               // 4cc1220b
	ADD	R19.UXTX, R14, R17              // d161338b
	ADDSW	R19.UXTW, R14, R17              // d141332b
	ADDS	R12.SXTX, R3, R1                // 61e02cab
	SUB	R19.UXTH<<4, R2, R21            // 553033cb
	SUBW	R1.UXTX<<1, R3, R2              // 6264214b

	VPEXTRW $127, X20, BP             // 62b17d08c5ec7f or 62e37d0815e57f or 62e3fd0815e57f
	VPEXTRW $17, X20, R14             // 62317d08c5f411 or 62c37d0815e611 or 62c3fd0815e611
	VPEXTRW $127, X20, R14            // 62317d08c5f47f or 62c37d0815e67f or 62c3fd0815e67f
	VPEXTRW $17, X20, (AX)            // 62e37d08152011 or 62e3fd08152011

		register[s] = int16(i + x86.REG_AL)
	}
	// Pseudo-registers.
	register["SB"] = RSB
	register["FP"] = RFP
	register["PC"] = RPC
	if linkArch == &x86.Linkamd64 {
		// Alias g to R14
		register["g"] = x86.REGG
	}
	// Register prefix not used on this architecture.

	instructions := make(map[string]obj.As)
	for i, s := range obj.Anames {
		instructions[s] = obj.As(i)
	}

TEXT errors(SB),$0
	AND	$1, RSP                                          // ERROR "illegal source register"
	ANDS	$1, R0, RSP                                      // ERROR "illegal combination"
	ADDSW	R7->32, R14, R13                                 // ERROR "shift amount out of range 0 to 31"
	ADD	R1.UXTB<<5, R2, R3                               // ERROR "shift amount out of range 0 to 4"