StringBuilder builder = new StringBuilder();
    Writer writer = new AppendableWriter(builder);

    writer.write("Hi");
    writer.close();

    assertThrows(IOException.class, () -> writer.write(" Greg"));

    assertThrows(IOException.class, () -> writer.flush());

    // close()ing already closed writer is allowed
    writer.close();
  }

nsw.edu.au
nt.edu.au
qld.edu.au
sa.edu.au
tas.edu.au
vic.edu.au
wa.edu.au
// act.gov.au  Bug 984824 - Removed at request of Greg Tankard
// nsw.gov.au  Bug 547985 - Removed at request of <******@****.***>
// nt.gov.au  Bug 940478 - Removed at request of Greg Connors <Greg******@****.***>
qld.gov.au
sa.gov.au
tas.gov.au
vic.gov.au
wa.gov.au
// 4LDs

	}

	if isIndex {
		arng_type, ok = loong64ElemExtMap[ext]
		if !ok {
			return errors.New("Loong64 extension: invalid LSX/LASX arrangement type: " + ext)
		}

		a.Reg = loong64.REG_ELEM
		a.Reg += ((reg & loong64.EXT_REG_MASK) << loong64.EXT_REG_SHIFT)
		a.Reg += ((arng_type & loong64.EXT_TYPE_MASK) << loong64.EXT_TYPE_SHIFT)

Kuang, Fei Hu, fo40225, formath, Fred Reiss, Frederic Bastien, Fredrik Knutsson,
G. Hussain Chinoy, Gabriel, gehring, George Grzegorz Pawelczak, Gianluca
Varisco, Gleb Popov, Greg Peatfield, Guillaume Klein, Gurpreet Singh, Gustavo
Lima Chaves, haison, Haraldur TóMas HallgríMsson, HarikrishnanBalagopal, HåKon
Sandsmark, I-Hong, Ilham Firdausi Putra, Imran Salam, Jason Zaman, Jason

	// Expect (SB), (FP), (PC), or (SP)
	p.get('(')
	reg := p.get(scanner.Ident).String()
	p.get(')')
	p.setPseudoRegister(a, reg, isStatic, prefix)
}

// setPseudoRegister sets the NAME field of addr for a pseudo-register reference such as (SB).
func (p *Parser) setPseudoRegister(addr *obj.Addr, reg string, isStatic bool, prefix rune) {
	if addr.Reg != 0 {
		p.errorf("internal error: reg %s already set in pseudo", reg)
	}
	switch reg {

        // Count how many registrations this affects
        int affectedRegistrations = 0;
        for (MockRegistration reg : registrations.values()) {
            if (reg.shareName.equalsIgnoreCase(resourceName) || reg.serverAddress.equals(resourceName)) {
                affectedRegistrations++;
            }
        }

			// the CR bit.
			prog.Reg = a[1].Reg
			if a[1].Type != obj.TYPE_REG {
				// The CR bit is represented as a constant 0-31. Convert it to a Reg.
				c := p.getConstant(prog, op, &a[1])
				reg, success := ppc64.ConstantToCRbit(c)
				if !success {
					p.errorf("invalid CR bit register number %d", c)
				}
				prog.Reg = reg
			}
			break
		}

        WitnessRegisterResponse mockResponse = mock(WitnessRegisterResponse.class);
        lenient().when(mockResponse.isSuccess()).thenReturn(true);
        lenient().when(mockResponse.getRegistrationId()).thenReturn("test-reg-123");

        WitnessRpcClient mockRpc = mock(WitnessRpcClient.class);
        lenient().when(mockRpc.register(any(WitnessRegisterRequest.class))).thenReturn(mockResponse);

        PlexusContainer mockedContainer = mock(PlexusContainer.class);
        when(mockedContainer.lookupMap(Lifecycle.class)).thenReturn(lifeCycles);

        DefaultLifecycleRegistry reg = new DefaultLifecycleRegistry();
        return new DefaultLifecycles(reg, new DefaultLookup(mockedContainer));
    }

}

// ARM64RegisterShift constructs an ARM64 register with shift operation.
func ARM64RegisterShift(reg, op, count int16) (int64, error) {
	// the base register of shift operations must be general register.
	if reg > arm64.REG_R31 || reg < arm64.REG_R0 {
		return 0, errors.New("invalid register for shift operation")
	}
	return int64(reg&31)<<16 | int64(op)<<22 | int64(uint16(count)), nil
}