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Results 1 - 10 of 24 for Greg (0.06 sec)

  1. licenses/github.com/gregjones/httpcache/LICENSE.txt

    Copyright © 2012 Greg Jones (greg******@****.***)
    
    Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the “Software”), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
    
    Registered: Wed Nov 06 22:53:10 UTC 2024
    - Last Modified: Sat Oct 26 02:47:39 UTC 2019
    - 1.1K bytes
    - Viewed (0)
  2. CITATION.cff

        given-names: Paul
      - family-names: Brevdo
        given-names: Eugene
      - family-names: Chen
        given-names: Zhifeng
      - family-names: Citro
        given-names: Craig
      - family-names: Corrado
        given-names: Greg S.
      - family-names: Davis
        given-names: Andy
      - family-names: Dean
        given-names: Jeffrey
      - family-names: Devin
        given-names: Matthieu
      - family-names: Ghemawat
        given-names: Sanjay
    Registered: Tue Nov 05 12:39:12 UTC 2024
    - Last Modified: Mon Sep 06 15:26:23 UTC 2021
    - 3.5K bytes
    - Viewed (0)
  3. guava-tests/test/com/google/common/io/AppendableWriterTest.java

        StringBuilder builder = new StringBuilder();
        Writer writer = new AppendableWriter(builder);
    
        writer.write("Hi");
        writer.close();
    
        assertThrows(IOException.class, () -> writer.write(" Greg"));
    
        assertThrows(IOException.class, () -> writer.flush());
    
        // close()ing already closed writer is allowed
        writer.close();
      }
    Registered: Fri Nov 01 12:43:10 UTC 2024
    - Last Modified: Wed Sep 06 17:04:31 UTC 2023
    - 3.2K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/mips64.s

    //	LFADD freg ',' freg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	ADDD	F1, F2
    
    //	LFADD freg ',' freg ',' freg
    //	{
    //		outcode(int($1), &$2, int($4.Reg), &$6);
    //	}
    	ADDD	F1, F2, F3
    
    //	LFCMP freg ',' freg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	CMPEQD	F1, F2
    
    
    //
    // WORD
    //
    	WORD	$1	// 00000001
    	NOOP		// 00000000
    	SYNC		// 0000000f
    
    //
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/mips.s

    	//	}
    	ADD	$4, R1
    
    	//	LMUL rreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	MUL	R1, R2
    
    	//	LSHW rreg ',' sreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, int($4), &$6);
    	//	}
    	SLL	R1, R2, R3
    
    	//	LSHW rreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	SLL	R1, R2
    
    	//	LSHW imm ',' sreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, int($4), &$6);
    	//	}
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 6.7K bytes
    - Viewed (0)
  6. okhttp/src/test/resources/okhttp3/internal/publicsuffix/public_suffix_list.dat

    nsw.edu.au
    nt.edu.au
    qld.edu.au
    sa.edu.au
    tas.edu.au
    vic.edu.au
    wa.edu.au
    // act.gov.au  Bug 984824 - Removed at request of Greg Tankard
    // nsw.gov.au  Bug 547985 - Removed at request of <******@****.***>
    // nt.gov.au  Bug 940478 - Removed at request of Greg Connors <Greg******@****.***>
    qld.gov.au
    sa.gov.au
    tas.gov.au
    vic.gov.au
    wa.gov.au
    // 4LDs
    Registered: Fri Nov 01 11:42:11 UTC 2024
    - Last Modified: Wed Dec 20 23:27:07 UTC 2023
    - 240.3K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/asm/testdata/arm.s

    // MULL r1,r2,(hi,lo)
    //
    //	LTYPEM cond reg ',' reg ',' regreg
    //	{
    //		outcode($1, $2, &$3, int32($5.Reg), &$7);
    //	}
    	MULL	R1, R2, (R3,R4)
    
    //
    // MULA r1,r2,r3,r4: (r1*r2+r3) & 0xffffffff . r4
    // MULAW{T,B} r1,r2,r3,r4
    //
    //	LTYPEN cond reg ',' reg ',' reg ',' spreg
    //	{
    //		$7.Type = obj.TYPE_REGREG2;
    //		$7.Offset = int64($9);
    //		outcode($1, $2, &$3, int32($5.Reg), &$7);
    //	}
    	MULAWT	R1, R2, R3, R4
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 69K bytes
    - Viewed (0)
  8. RELEASE.md

    Kuang, Fei Hu, fo40225, formath, Fred Reiss, Frederic Bastien, Fredrik Knutsson,
    G. Hussain Chinoy, Gabriel, gehring, George Grzegorz Pawelczak, Gianluca
    Varisco, Gleb Popov, Greg Peatfield, Guillaume Klein, Gurpreet Singh, Gustavo
    Lima Chaves, haison, Haraldur TóMas HallgríMsson, HarikrishnanBalagopal, HåKon
    Sandsmark, I-Hong, Ilham Firdausi Putra, Imran Salam, Jason Zaman, Jason
    Registered: Tue Nov 05 12:39:12 UTC 2024
    - Last Modified: Tue Oct 22 14:33:53 UTC 2024
    - 735.3K bytes
    - Viewed (0)
  9. src/cmd/asm/internal/asm/parse.go

    	// Expect (SB), (FP), (PC), or (SP)
    	p.get('(')
    	reg := p.get(scanner.Ident).String()
    	p.get(')')
    	p.setPseudoRegister(a, reg, isStatic, prefix)
    }
    
    // setPseudoRegister sets the NAME field of addr for a pseudo-register reference such as (SB).
    func (p *Parser) setPseudoRegister(addr *obj.Addr, reg string, isStatic bool, prefix rune) {
    	if addr.Reg != 0 {
    		p.errorf("internal error: reg %s already set in pseudo", reg)
    	}
    	switch reg {
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Sep 04 18:16:59 UTC 2024
    - 36.9K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/arch/arm64.go

    		}
    	} else if reg <= arm64.REG_V31 && reg >= arm64.REG_V0 {
    		switch ext {
    		case "B8":
    			if isIndex {
    				return errors.New("invalid register extension")
    			}
    			a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8B & 15) << 5)
    		case "B16":
    			if isIndex {
    				return errors.New("invalid register extension")
    			}
    			a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_16B & 15) << 5)
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Thu Sep 29 09:04:58 UTC 2022
    - 10.4K bytes
    - Viewed (0)
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