}
	word, cond = p.lex.Text(), ""
	operands = scratch[:0]
	// Zero or more comma-separated operands, one per loop.
	nesting := 0
	colon := -1
	for tok != '\n' && tok != ';' {
		// Process one operand.
		var items []lex.Token
		if cap(operands) > len(operands) {
			// Reuse scratch items slice.
			items = operands[:cap(operands)][len(operands)][:0]
		} else {
			items = make([]lex.Token, 0, 3)
		}

// GLOBL shifts<>(SB),$256
func (p *Parser) asmGlobl(operands [][]lex.Token) {
	if len(operands) != 2 && len(operands) != 3 {
		p.errorf("expect two or three operands for GLOBL")
		return
	}

	// Operand 0 has the general form foo<>+0x04(SB).
	nameAddr := p.address(operands[0])
	if !p.validSymbol("GLOBL", &nameAddr, false) {
		return
	}
	next := 1

	// Next operand is the optional flag, a literal integer.

		}
		// Add the CSRs
		for csrCode, csrName := range riscv.CSRs {
			// The set of RVV special operand names and the set of CSR special operands
			// names are disjoint and so can safely share a single namespace. However,
			// it's possible that a future update to the CSRs in inst.go could introduce
			// a conflict. This check ensures that such a conflict does not go
			// unnoticed.
			if _, ok := riscv64SpecialOperand[csrName]; ok {

	VMERGEVIM	$15, V2, V4, V3			// ERROR "invalid vector mask register"
	VMVVV		V1, V2, V3			// ERROR "too many operands for instruction"
	VMVVX		X10, V2, V3			// ERROR "too many operands for instruction"
	VMVVI		$15, V2, V3			// ERROR "too many operands for instruction"
	VSADDUVV	V1, V2, V4, V3			// ERROR "invalid vector mask register"
	VSADDUVX	X10, V2, V4, V3			// ERROR "invalid vector mask register"

</pre>

<h2 id="Expressions">Expressions</h2>

<p>
An expression specifies the computation of a value by applying
operators and functions to operands.
</p>

<h3 id="Operands">Operands</h3>

<p>
Operands denote the elementary values in an expression. An operand may be a
literal, a (possibly <a href="#Qualified_identifiers">qualified</a>)
non-<a href="#Blank_identifier">blank</a> identifier denoting a

	VMOV	V8.D[0], V12.S[1]                                // ERROR "operand mismatch"
	VMOV	V8.D[0], V12.H[1]                                // ERROR "operand mismatch"
	VMOV	V8.D[0], V12.B[1]                                // ERROR "operand mismatch"
	VMOV	V8.S[0], V12.H[1]                                // ERROR "operand mismatch"
	VMOV	V8.S[0], V12.B[1]                                // ERROR "operand mismatch"

	// Pseudo-registers.
	register["SB"] = RSB
	register["FP"] = RFP
	register["PC"] = RPC
	register["SP"] = RSP
	registerPrefix := map[string]bool{
		"F": true,
		"R": true,
	}

	// special operands for DMB/DSB instructions
	register["MB_SY"] = arm.REG_MB_SY
	register["MB_ST"] = arm.REG_MB_ST
	register["MB_ISH"] = arm.REG_MB_ISH
	register["MB_ISHST"] = arm.REG_MB_ISHST
	register["MB_NSH"] = arm.REG_MB_NSH

	VMOVQ (AX), X20           // 62e1fd086e20 or 62e1fe087e20
	VMOVQ 7(DX), X20          // 62e1fd086ea207000000 or 62e1fe087ea207000000
	VMOVQ -15(R11)(CX*1), X20 // 62c1fd086ea40bf1ffffff or 62c1fe087ea40bf1ffffff
	VMOVQ (SP)(AX*2), X20     // 62e1fd086e2444 or 62e1fe087e2444
	// "VMOVQ xmm1, r/m64"/7E vs "VMOVQ xmm1, xmm2/m64"/D6 with mem operand.

		selectAST.Expression.Expressions[0].Expression.And[0].Condition[0].Operand != nil &&
		selectAST.Expression.Expressions[0].Expression.And[0].Condition[0].Operand.Operand.Left != nil &&
		selectAST.Expression.Expressions[0].Expression.And[0].Condition[0].Operand.Operand.Left.Left != nil &&
		selectAST.Expression.Expressions[0].Expression.And[0].Condition[0].Operand.Operand.Left.Left.Primary != nil &&

	if e.ConditionRHS == nil {
		result = e.Operand.analyze(s)
	} else {
		result.combine(e.Operand.analyze(s))
		result.combine(e.ConditionRHS.analyze(s))
	}
	return result
}

func (e *ConditionRHS) analyze(s *Select) (result qProp) {
	switch {
	case e.Compare != nil:
		result = e.Compare.Operand.analyze(s)
	case e.Between != nil:
		result.combine(e.Between.Start.analyze(s))