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Results 1 - 10 of 21 for mfvscr (0.14 sec)

  1. src/cmd/vendor/rsc.io/markdown/entity.go

    	"▪":           "\u25aa",
    	"𝔽":                            "\U0001d53d",
    	"∀":                          "\u2200",
    	"ℱ":                      "\u2131",
    	"ℱ":                            "\u2131",
    	"Ѓ":                            "\u0403",
    	">":                              "\u003e",
    	"Γ":                           "\u0393",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Jan 24 13:01:26 UTC 2024
    - 101K bytes
    - Viewed (0)
  2. src/internal/bytealg/compare_ppc64x.s

    	VPERM	V3,V3,SWAP,V3
    	VPERM	V4,V4,SWAP,V4
    #endif
    
    	MFVSRD	VS35,R16	// move upper doublewords of A and B into GPR for comparison
    	MFVSRD	VS36,R10
    
    	CMPU	R16,R10
    	BEQ	lower
    	SETB_CR0_NE(R3)
    	RET
    
    	PCALIGN $16
    lower:
    	VSLDOI	$8,V3,V3,V3	// move lower doublewords of A and B into GPR for comparison
    	MFVSRD	VS35,R16
    	VSLDOI	$8,V4,V4,V4
    	MFVSRD	VS36,R10
    
    	CMPU	R16,R10
    	SETB_CR0_NE(R3)
    	RET
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Aug 28 17:33:20 UTC 2023
    - 6.7K bytes
    - Viewed (0)
  3. src/internal/bytealg/count_ppc64x.s

    	VADDUDM	V0, V4, V4	// Accumulate the popcounts. They are 8x the count.
    	VADDUDM	V2, V5, V5	// The count will be fixed up afterwards.
    	ADD	$32, R3
    	BDNZ	cmploop
    
    	VADDUDM	V4, V5, V5
    	MFVSRD	V5, R18
    	VSLDOI	$8, V5, V5, V5
    	MFVSRD	V5, R21
    	ADD	R21, R18, R18
    	ANDCC	$31, R4, R4
    	// Skip the tail processing if no bytes remaining.
    	BEQ	tail_0
    
    #ifdef GOPPC64_power10
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Aug 14 20:30:44 UTC 2023
    - 3.6K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/ppc64/anames9.go

    	"U16CON",
    	"16CON",
    	"U31CON",
    	"S32CON",
    	"U32CON",
    	"32CON",
    	"S34CON",
    	"64CON",
    	"SACON",
    	"LACON",
    	"DACON",
    	"BRA",
    	"BRAPIC",
    	"ZOREG",
    	"SOREG",
    	"LOREG",
    	"XOREG",
    	"FPSCR",
    	"LR",
    	"CTR",
    	"ANY",
    	"GOK",
    	"ADDR",
    	"TLS_LE",
    	"TLS_IE",
    	"TEXTSIZE",
    	"NCLASS",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 09 22:14:57 UTC 2024
    - 673 bytes
    - Viewed (0)
  5. src/runtime/signal_aix_ppc64.go

    func (c *sigctxt) link() uint64   { return c.regs().lr }
    func (c *sigctxt) xer() uint32    { return c.regs().xer }
    func (c *sigctxt) ccr() uint32    { return c.regs().cr }
    func (c *sigctxt) fpscr() uint32  { return c.regs().fpscr }
    func (c *sigctxt) fpscrx() uint32 { return c.regs().fpscrx }
    
    // TODO(aix): find trap equivalent
    func (c *sigctxt) trap() uint32 { return 0x0 }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 15 21:57:36 UTC 2023
    - 3.5K bytes
    - Viewed (0)
  6. src/cmd/internal/obj/ppc64/anames.go

    	"LXVX",
    	"LXVDSX",
    	"STXV",
    	"STXVL",
    	"STXVLL",
    	"STXVD2X",
    	"STXVW4X",
    	"STXVH8X",
    	"STXVB16X",
    	"STXVX",
    	"LXSDX",
    	"STXSDX",
    	"LXSIWAX",
    	"LXSIWZX",
    	"STXSIWX",
    	"MFVSRD",
    	"MFFPRD",
    	"MFVRD",
    	"MFVSRWZ",
    	"MFVSRLD",
    	"MTVSRD",
    	"MTFPRD",
    	"MTVRD",
    	"MTVSRWA",
    	"MTVSRWZ",
    	"MTVSRDD",
    	"MTVSRWS",
    	"XXLAND",
    	"XXLANDC",
    	"XXLEQV",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 6.7K bytes
    - Viewed (0)
  7. src/runtime/defs_windows_arm.go

    	r7           uint32
    	r8           uint32
    	r9           uint32
    	r10          uint32
    	r11          uint32
    	r12          uint32
    
    	spr  uint32
    	lrr  uint32
    	pc   uint32
    	cpsr uint32
    
    	fpscr   uint32
    	padding uint32
    
    	floatNeon [16]neon128
    
    	bvr      [8]uint32
    	bcr      [8]uint32
    	wvr      [1]uint32
    	wcr      [1]uint32
    	padding2 [2]uint32
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 05 08:26:52 UTC 2023
    - 2.6K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/asm/testdata/mips.s

    	//	}
    	MOVD	F1, foo<>+3(SB)
    	MOVD	F1, 16(R2)
    	MOVD	F1, (R2)
    
    	//
    	// floating point status
    	//
    	//	LMOVW fpscr ',' freg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	MOVW	FCR0, R1
    
    	//	LMOVW freg ','  fpscr
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	MOVW	R1, FCR0
    
    	//	LMOVW rreg ',' mreg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 6.7K bytes
    - Viewed (0)
  9. src/runtime/mkpreempt.go

    	for i := 0; i <= 31; i++ {
    		reg := fmt.Sprintf("F%d", i)
    		l.add("FMOVD", reg, 8)
    	}
    	// Add floating point control/status register FPSCR.
    	l.addSpecial(
    		"MOVFL FPSCR, F0\nFMOVD F0, %d(R1)",
    		"FMOVD %d(R1), F0\nMOVFL F0, FPSCR",
    		8)
    
    	p("MOVD R31, -%d(R1)", l.stack-32) // save R31 first, we'll use R31 for saving LR
    	p("MOVD LR, R31")
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 15.3K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/asm/testdata/mips64.s

    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	MOVD	F1, foo<>+3(SB)
    	MOVD	F1, 16(R2)
    	MOVD	F1, (R2)
    
    //
    // floating point status
    //
    //	LMOVW fpscr ',' freg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	MOVW	FCR31, R1 // 4441f800
    
    //	LMOVW freg ','  fpscr
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	MOVW	R1, FCR31 // 44c1f800
    
    //	LMOVW rreg ',' mreg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
    - Viewed (0)
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