func (c *sigctxt) link() uint64   { return c.regs().lr }
func (c *sigctxt) xer() uint32    { return c.regs().xer }
func (c *sigctxt) ccr() uint32    { return c.regs().cr }
func (c *sigctxt) fpscr() uint32  { return c.regs().fpscr }
func (c *sigctxt) fpscrx() uint32 { return c.regs().fpscrx }

// TODO(aix): find trap equivalent
func (c *sigctxt) trap() uint32 { return 0x0 }

func (c *sigctxt) sigcode() uint32 { return uint32(c.info.si_code) }

}

type context64 struct {
	gpr        [32]uint64
	msr        uint64
	iar        uint64
	lr         uint64
	ctr        uint64
	cr         uint32
	xer        uint32
	fpscr      uint32
	fpscrx     uint32
	except     [1]uint64
	fpr        [32]float64
	fpeu       uint8
	fpinfo     uint8
	fpscr24_31 uint8
	pad        [1]uint8
	excp_type  int32
}

type sigactiont struct {

	for i := 0; i <= 31; i++ {
		reg := fmt.Sprintf("F%d", i)
		l.add("FMOVD", reg, 8)
	}
	// Add floating point control/status register FPSCR.
	l.addSpecial(
		"MOVFL FPSCR, F0\nFMOVD F0, %d(R1)",
		"FMOVD %d(R1), F0\nMOVFL F0, FPSCR",
		8)

	p("MOVD R31, -%d(R1)", l.stack-32) // save R31 first, we'll use R31 for saving LR
	p("MOVD LR, R31")

	if REG_R0 <= r && r <= REG_R15 {
		return fmt.Sprintf("R%d", r-REG_R0)
	}
	if REG_F0 <= r && r <= REG_F15 {
		return fmt.Sprintf("F%d", r-REG_F0)
	}

	switch r {
	case REG_FPSR:
		return "FPSR"

	case REG_FPCR:
		return "FPCR"

	case REG_CPSR:
		return "CPSR"

	case REG_SPSR:
		return "SPSR"

	case REG_MB_SY:
		return "MB_SY"
	case REG_MB_ST:
		return "MB_ST"
	case REG_MB_ISH:
		return "MB_ISH"

	"U16CON",
	"16CON",
	"U31CON",
	"S32CON",
	"U32CON",
	"32CON",
	"S34CON",
	"64CON",
	"SACON",
	"LACON",
	"DACON",
	"BRA",
	"BRAPIC",
	"ZOREG",
	"SOREG",
	"LOREG",
	"XOREG",
	"FPSCR",
	"LR",
	"CTR",
	"ANY",
	"GOK",
	"ADDR",
	"TLS_LE",
	"TLS_IE",
	"TEXTSIZE",
	"NCLASS",

	D25
	D26
	D27
	D28
	D29
	D30
	D31

	APSR
	APSR_nzcv
	FPSCR

	SP = R13
	LR = R14
	PC = R15
)

func (Reg) IsArg() {}

func (r Reg) String() string {
	switch r {
	case APSR:
		return "APSR"
	case APSR_nzcv:
		return "APSR_nzcv"
	case FPSCR:
		return "FPSCR"
	case SP:
		return "SP"
	case PC:
		return "PC"
	case LR:
		return "LR"

	pc    uint64     // program counter
	cpsr  uint32     // current program status register
	__pad uint32
}

type neonstate64 struct {
	v    [64]uint64 // actually [32]uint128
	fpsr uint32
	fpcr uint32
}

type mcontext64 struct {
	es exceptionstate64
	ss regs64
	ns neonstate64
}

type ucontext struct {
	uc_onstack  int32
	uc_sigmask  uint32
	uc_stack    stackt

	FMOVD F25, 456(R1)
	FMOVD F26, 464(R1)
	FMOVD F27, 472(R1)
	FMOVD F28, 480(R1)
	FMOVD F29, 488(R1)
	FMOVD F30, 496(R1)
	FMOVD F31, 504(R1)
	MOVFL FPSCR, F0
	FMOVD F0, 512(R1)
	CALL ·asyncPreempt2(SB)
	FMOVD 512(R1), F0
	MOVFL F0, FPSCR
	FMOVD 504(R1), F31
	FMOVD 496(R1), F30
	FMOVD 488(R1), F29
	FMOVD 480(R1), F28
	FMOVD 472(R1), F27
	FMOVD 464(R1), F26
	FMOVD 456(R1), F25
	FMOVD 448(R1), F24

type context struct {
	contextflags uint32
	cpsr         uint32
	x            [31]uint64 // fp is x[29], lr is x[30]
	xsp          uint64
	pc           uint64
	v            [32]neon128
	fpcr         uint32
	fpsr         uint32
	bcr          [8]uint32
	bvr          [8]uint64
	wcr          [2]uint32
	wvr          [2]uint64
}

func (c *context) ip() uintptr { return uintptr(c.pc) }

func fpRegAddr(dst *sigcontext, i int) *uint64 {
	/* FP-SIMD registers are saved in sigcontext.__reserved, which is orgnized in
	the following C structs:
	struct fpsimd_context {
		struct _aarch64_ctx head;
		__u32 fpsr;
		__u32 fpcr;
		__uint128_t vregs[32];
	};
	struct _aarch64_ctx {
		__u32 magic;
		__u32 size;
	};
	So the offset of the ith FP_SIMD register is 16+i*128.
	*/