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Results 1 - 10 of 11 for R0 (0.09 sec)
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src/cmd/asm/internal/asm/testdata/armerror.s
MOVB F0, R0 // ERROR "illegal combination" MOVH F0, R0 // ERROR "illegal combination" MOVB R0, F0 // ERROR "illegal combination" MOVH R0, F0 // ERROR "illegal combination" MOVB R0>>0(R1), R2 // ERROR "bad shift" MOVB R0->0(R1), R2 // ERROR "bad shift" MOVB R0@>0(R1), R2 // ERROR "bad shift" MOVBS R0>>0(R1), R2 // ERROR "bad shift"
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Oct 23 15:18:14 UTC 2024 - 14.5K bytes - Viewed (0) -
android/guava-tests/test/com/google/common/util/concurrent/RateLimiterTest.java
limiter.acquire(); // #7 } assertEvents( "R0.00, R1.38, R1.13, R0.88, R0.63, R0.50, R0.50, R0.50", // #1 "U0.50", // #2 "U4.00", // #3 "R0.00, R1.38, R1.13, R0.88, R0.63, R0.50, R0.50, R0.50", // #4 "U0.50", // #5 "U2.00", // #6 "R0.00, R0.50, R0.50, R0.50, R0.50, R0.50, R0.50, R0.50"); // #7 } public void testWarmUpWithColdFactor() {
Registered: Fri Sep 05 12:43:10 UTC 2025 - Last Modified: Mon Aug 11 19:31:30 UTC 2025 - 21.9K bytes - Viewed (0) -
guava-tests/test/com/google/common/util/concurrent/RateLimiterTest.java
limiter.acquire(); // #7 } assertEvents( "R0.00, R1.38, R1.13, R0.88, R0.63, R0.50, R0.50, R0.50", // #1 "U0.50", // #2 "U4.00", // #3 "R0.00, R1.38, R1.13, R0.88, R0.63, R0.50, R0.50, R0.50", // #4 "U0.50", // #5 "U2.00", // #6 "R0.00, R0.50, R0.50, R0.50, R0.50, R0.50, R0.50, R0.50"); // #7 } public void testWarmUpWithColdFactor() {
Registered: Fri Sep 05 12:43:10 UTC 2025 - Last Modified: Mon Aug 11 19:31:30 UTC 2025 - 21.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
ADRP 12(PC), R2 // 02000090 // LDP/STP LDP (R0), (R0, R1) // 000440a9 LDP (R0), (R1, R2) // 010840a9 LDP 8(R0), (R1, R2) // 018840a9 LDP -8(R0), (R1, R2) // 01887fa9 LDP 11(R0), (R1, R2) // 1b2c0091610b40a9 LDP 1024(R0), (R1, R2) // 1b001091610b40a9 LDP.W 8(R0), (R1, R2) // 0188c0a9 LDP.P 8(R0), (R1, R2) // 0188c0a8 LDP (RSP), (R1, R2) // e10b40a9
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Mar 26 10:48:50 UTC 2025 - 95.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
CMP R3, R0 // 7c230000 CMP R3, R0, CR1 // CMP R3,CR1,R0 // 7ca30000 CMPU R3, R4 // 7c232040 CMPU R3, R0 // 7c230040 CMPU R3, R0, CR2 // CMPU R3,CR2,R0 // 7d230040 CMPW R3, R4 // 7c032000 CMPW R3, R0 // 7c030000 CMPW R3, R0, CR3 // CMPW R3,CR3,R0 // 7d830000
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Thu Nov 21 18:27:17 UTC 2024 - 51.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
RXSBGT $17, $8, $16, R9, R10 // eca991081057 ROSBGT $9, $24, $11, R11, R0 // ec0b89180b56 RISBG $0, $31, $32, R1, R2 // ec21001f2055 RISBGN $17, $8, $16, R3, R4 // ec4311081059 RISBGZ $9, $24, $11, R5, R6 // ec6509980b55 RISBGNZ $0, $31, $32, R7, R8 // ec87009f2059 RISBHG $17, $8, $16, R9, R10 // eca91108105d RISBLG $9, $24, $11, R11, R0 // ec0b09180b51 RISBHGZ $17, $8, $16, R9, R10 // eca91188105d
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Jul 30 19:29:15 UTC 2025 - 22.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64error.s
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Mar 26 10:48:50 UTC 2025 - 37.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/parse.go
return 10 } if name[0] != 'R' { p.errorf("expected g or R0 through R15; found %s", name) return 0 } r, ok := p.registerReference(name) if !ok { return 0 } reg := r - p.arch.Register["R0"] if reg < 0 { // Could happen for an architecture having other registers prefixed by R p.errorf("expected g or R0 through R15; found %s", name) return 0 } return uint16(reg) }
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Fri Feb 14 15:13:11 UTC 2025 - 37.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
ROTRV $4, R4 // 84104d00 SYSCALL // 00002b00 BEQ R4, R5, 1(PC) // 85040058 BEQ R4, 1(PC) // 80040040 BEQ R4, R0, 1(PC) // 80040040 BEQ R0, R4, 1(PC) // 80040040 BNE R4, R5, 1(PC) // 8504005c BNE R4, 1(PC) // 80040044 BNE R4, R0, 1(PC) // 80040044 BNE R0, R4, 1(PC) // 80040044 BLTU R4, 1(PC) // 80040068 MOVF y+8(FP), F4 // 6440002b MOVD y+8(FP), F4 // 6440802b
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Thu Sep 04 19:24:25 UTC 2025 - 35.5K bytes - Viewed (0) -
lib/fips140/v1.0.0.zip
addMul64(r0, a1_19, b4) r0 = addMul64(r0, a2_19, b3) r0 = addMul64(r0, a3_19, b2) r0 = addMul64(r0, a4_19, b1) // r1 = a0×b1 + a1×b0 + 19×(a2×b4 + a3×b3 + a4×b2) r1 := mul64(a0, b1) r1 = addMul64(r1, a1, b0) r1 = addMul64(r1, a2_19, b4) r1 = addMul64(r1, a3_19, b3) r1 = addMul64(r1, a4_19, b2) // r2 = a0×b2 + a1×b1 + a2×b0 + 19×(a3×b4 + a4×b3) r2 := mul64(a0, b2) r2 = addMul64(r2, a1, b1) r2 = addMul64(r2, a2, b0) r2 = addMul64(r2, a3_19, b4) r2 = addMul64(r2, a4_19, b3) // r3 = a0×b3 + a1×b2 + a2×b1...
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Jan 29 15:10:35 UTC 2025 - 635K bytes - Viewed (0)