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src/cmd/asm/internal/asm/testdata/ppc64_p10.s
PLHA 1234(R1), $0, R3 // 06000000a86104d2 PLHZ 1234(R1), $0, R3 // 06000000a06104d2 PLQ 1234(R1), $0, R4 // 04000000e08104d2 PLWA 1234(R1), $0, R3 // 04000000a46104d2 PLWZ 1234567890(R4), $0, R3 // 06004996806402d2 PLWZ 1234567890(R0), $1, R3 // 06104996806002d2 PLXSD 1234(R1), $0, V1 // 04000000a82104d2
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Thu Mar 23 20:52:57 GMT 2023 - 14.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64error.s
MOVF $8(SP), X5 // ERROR "unsupported address load" MOV $1234, 0(SP) // ERROR "constant load must target register" MOV $1234, 8(SP) // ERROR "constant load must target register" MOV $0, 0(SP) // ERROR "constant load must target register" MOV $0, 8(SP) // ERROR "constant load must target register" MOV $1234, 0(SP) // ERROR "constant load must target register" MOV $1234, 8(SP) // ERROR "constant load must target register"
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Sun Apr 07 03:32:27 GMT 2024 - 2.8K bytes - Viewed (0) -
common/scripts/metallb-native.yaml
communities: description: The BGP communities to be associated with the announcement. Each item can be a standard community of the form 1234:1234, a large community of the form large:1234:1234:1234 or the name of an alias defined in the Community CRD. items: type: string type: array
Others - Registered: Wed May 08 22:53:08 GMT 2024 - Last Modified: Fri Feb 23 23:56:31 GMT 2024 - 63.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
// outcode($1, $2, &$5, int32($3.Reg), &$7); // } STREX R1, (R2), R3 // STREX (R2), R1, R3 // // word // // LTYPEH comma ximm // { // outcode($1, Always, &nullgen, 0, &$3); // } WORD $1234 // // floating-point coprocessor // // LTYPEI cond freg ',' freg // { // outcode($1, $2, &$3, 0, &$5); // } ABSF F1, F2 // LTYPEK cond frcon ',' freg // {
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 15 20:51:01 GMT 2023 - 69K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
// 12.3: Double-Precision Load and Store Instructions FLD (X5), F0 // 07b00200 FLD 4(X5), F0 // 07b04200 FSD F0, (X5) // 27b00200 FSD F0, 4(X5) // 27b20200 // 12.4: Double-Precision Floating-Point Computational Instructions FADDD F1, F0, F2 // 53011002 FSUBD F1, F0, F2 // 5301100a FMULD F1, F0, F2 // 53011012 FDIVD F1, F0, F2 // 5301101a
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Mar 22 04:42:21 GMT 2024 - 16.7K bytes - Viewed (1)