VFMLS	V1.D2, V12.D2, V1.D2            // 81cde14e
	VFMLS	V1.S2, V12.S2, V1.S2            // 81cda10e
	VFMLS	V1.S4, V12.S4, V1.S4            // 81cda14e
	VEXT	$4, V2.B8, V1.B8, V3.B8         // 2320022e
	VEXT	$8, V2.B16, V1.B16, V3.B16      // 2340026e
	VRBIT	V24.B16, V24.B16                // 185b606e
	VRBIT	V24.B8, V24.B8                  // 185b602e
	VUSHR	$56, V1.D2, V2.D2               // 2204486f

// In case of index mode instructions, usage of
// (Rx)(R0) is equivalent to (Rx+R0)
// In case of base+displacement mode instructions if
// the offset is 0, usage of (Rx) is equivalent to 0(Rx)
TEXT asmtest(SB),DUPOK|NOSPLIT,$0
	// move constants
	MOVD $1, R3                     // 38600001
	MOVD $-1, R4                    // 3880ffff
	MOVD $65535, R5                 // 6005ffff

// Copyright 2021 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

TEXT errors(SB),$0
	MOV	$errors(SB), (X5)		// ERROR "address load must target register"
	MOV	$8(SP), (X5)			// ERROR "address load must target register"
	MOVB	$8(SP), X5			// ERROR "unsupported address load"
	MOVH	$8(SP), X5			// ERROR "unsupported address load"

// the old assembler's (5a's) grammar and hand-writing complete
// instructions for each rule, to guarantee we cover the same space.

#include "../../../../../runtime/textflag.h"

TEXT	foo(SB), DUPOK|NOSPLIT, $0

// ADD
//
//	LTYPE1 cond imsr ',' spreg ',' reg
//	{
//		outcode($1, $2, &$3, $5, &$7);
//	}
// Cover some operand space here too.
	ADD	$1, R2, R3
	ADD	R1<<R2, R3, R4

	REV8	X7, X8					// 13d4836b

	// 1.5: Single-bit Instructions (Zbs)
	BCLR	X23, X24, X25				// b31c7c49
	BCLR	$63, X24				// 131cfc4b
	BCLRI	$1, X25, X26				// 139d1c48
	BEXT	X26, X28, X29				// b35eae49
	BEXT	$63, X28				// 135efe4b
	BEXTI	$1, X29, X30				// 13df1e48
	BINV	X30, X5, X6				// 3393e269
	BINV	$63, X6					// 1313f36b
	BINVI	$1, X7, X8				// 13941368
	BSET	X8, X9, X10				// 33958428

	VPMULL2	V1.D1, V2.D1, V3.Q1                              // ERROR "operand mismatch"
	VPMULL2	V1.B8, V2.B8, V3.H8                              // ERROR "operand mismatch"
	VEXT	$8, V1.B16, V2.B8, V2.B16                        // ERROR "invalid arrangement"
	VEXT	$8, V1.H8, V2.H8, V2.H8                          // ERROR "invalid arrangement"
	VRBIT	V1.B16, V2.B8                                    // ERROR "invalid arrangement"

      label: "What did you see happen?"
      description: Command invocations and their associated output, functions with their arguments and return results, full stacktraces for panics (upload a file if it is very long), etc. Prefer copying text output over using screenshots.
    validations:
      required: true

  - type: textarea
    id: expected-behavior
    attributes:
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