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src/cmd/asm/internal/asm/testdata/mips64.s
MOVW R1, M1 // 40810800 MOVV R1, M1 // 40a10800 // LMOVW mreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MOVW M1, R1 // 40010800 MOVV M1, R1 // 40210800 // // integer operations // logical instructions // shift instructions // unary instructions // // LADDW rreg ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // } ADD R5, R9, R10 // 01255020
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 12.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
// instructions for each rule, to guarantee we cover the same space. #include "../../../../../runtime/textflag.h" TEXT foo(SB), DUPOK|NOSPLIT, $-8 // arithmetic operations ADDW $1, R2, R3 ADDW R1, R2, R3 ADDW R1, ZR, R3 ADD $1, R2, R3 ADD R1, R2, R3 ADD R1, ZR, R3 ADD $1, R2, R3 ADDW $1, R2 ADDW R1, R2 ADD $1, R2 ADD R1, R2 ADD R1>>11, R2
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 08 03:28:17 GMT 2023 - 94.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
// } MOVW R1, M1 MOVW R1, M1 // LMOVW mreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MOVW M1, R1 MOVW M1, R1 // // integer operations // logical instructions // shift instructions // unary instructions // // LADDW rreg ',' sreg ',' rreg // { // outcode(int($1), &$2, int($4), &$6); // } ADD R1, R2, R3
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 6.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
// 5.3: Load and Store Instructions (RV64I) LD (X5), X6 // 03b30200 LD 4(X5), X6 // 03b34200 SD X5, (X6) // 23305300 SD X5, 4(X6) // 23325300 // 7.1: Multiplication Operations MUL X5, X6, X7 // b3035302 MULH X5, X6, X7 // b3135302 MULHU X5, X6, X7 // b3335302 MULHSU X5, X6, X7 // b3235302 MULW X5, X6, X7 // bb035302 DIV X5, X6, X7 // b3435302
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Mar 22 04:42:21 GMT 2024 - 16.7K bytes - Viewed (1) -
src/cmd/asm/internal/asm/testdata/arm.s
// g.Offset = int64( // (0xe << 24) | /* opcode */ // ($1 << 20) | /* MCR/MRC */ // (($2^C_SCOND_XOR) << 28) | /* scond */ // (($3 & 15) << 8) | /* coprocessor number */ // (($5 & 7) << 21) | /* coprocessor operation */ // (($7 & 15) << 12) | /* arm register */ // (($9 & 15) << 16) | /* Crn */ // (($11 & 15) << 0) | /* Crm */ // (($12 & 7) << 5) | /* coprocessor information */ // (1<<4)); /* must be set */
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 15 20:51:01 GMT 2023 - 69K bytes - Viewed (0)