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Results 1 - 1 of 1 for XCHGL (0.09 sec)

  1. src/cmd/compile/internal/ssa/_gen/AMD64.rules

    	(XCHGQ [off1+off2] {mergeSym(sym1,sym2)} val ptr mem)
    (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) =>
    	(XCHGL [off1+off2] {sym} val ptr mem)
    (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && ptr.Op != OpSB =>
    	(XCHGL [off1+off2] {mergeSym(sym1,sym2)} val ptr mem)
    
    // Merge ADDQconst into atomic adds.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 93.9K bytes
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