(RSB (SRL y z) x) => (SUBshiftRLreg x y z)
(RSB x (SRA y z)) => (RSBshiftRAreg x y z)
(RSB (SRA y z) x) => (SUBshiftRAreg x y z)
(AND x (SLLconst [c] y)) => (ANDshiftLL x y [c])
(AND x (SRLconst [c] y)) => (ANDshiftRL x y [c])
(AND x (SRAconst [c] y)) => (ANDshiftRA x y [c])
(AND x (SLL y z)) => (ANDshiftLLreg x y z)
(AND x (SRL y z)) => (ANDshiftRLreg x y z)
(AND x (SRA y z)) => (ANDshiftRAreg x y z)

	SRA.S	$31, R5, R6          // c56fb0e1
	SRA	$14, R5              // 4557a0e1
	SRA	$15, R5              // c557a0e1
	SRA	$30, R5              // 455fa0e1
	SRA	$31, R5              // c55fa0e1
	SRA.S	$14, R5              // 4557b0e1
	SRA.S	$15, R5              // c557b0e1
	SRA.S	$30, R5              // 455fb0e1
	SRA.S	$31, R5              // c55fb0e1
	SRA	R5, R6, R7           // 5675a0e1
	SRA.S	R5, R6, R7           // 5675b0e1

//   result = arg >> (shift >= 64 ? 63 : shift)
(Rsh(64|32)x64 x y) => (SRA(D|W) x (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPUconst  y [64])))
(Rsh(64|32)x32 x y) => (SRA(D|W) x (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPWUconst y [64])))
(Rsh(64|32)x16 x y) => (SRA(D|W) x (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPWUconst (MOVHZreg y) [64])))

		{name: "SRLconst", argLength: 1, reg: gp11, asm: "LSR", aux: "Int64"},     // arg0 >> auxInt, unsigned, auxInt should be in the range 0 to 63.
		{name: "SRA", argLength: 2, reg: gp21, asm: "ASR"},                        // arg0 >> arg1, signed, shift amount is mod 64